參數(shù)資料
型號: AK2307
廠商: Asahi Kasei Microsystems Co.,Ltd
元件分類: Codec
英文描述: SPEECH CODEC for Digital Key telephone (5.0V/3.3V)
中文描述: 語音編解碼器的數(shù)字按鍵電話(5.0V/3.3V)
文件頁數(shù): 11/39頁
文件大?。?/td> 468K
代理商: AK2307
ASAHI KASEI [AK2307/LV]
2-2 Timing and format of the PCM interface
2-2-1 u/A-Law PCM data Mode
8 bits PCM data is accommodated in 1 frame( 125us ) defined by 8kHz frame sync signal.
Although there are 32 time slots at maximum in 8kHz frame(when BCK=2.048MHz), PCM data for AK2307/LV occupies
first time slot as is indicated in figures below.
2-2-1-a Signals
- Frame Sync signal (FS)
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface. All the internal
clock
of the LSI is generated based on this FS signal.
- Bit Clock (BCLK)
BCLK defines the PCM data rate. BCLK can be varied from 64kHz to 2.048MHz by 64kHz step.
- PCM data output (DX)
DX is an output signal of 64Kbps PCM u/A-law data. The data is synchronized to the BCLK which determines the data
rate. The period which the PCM data is not occupied, the DX pin turns to Hi -impedance output. In the long frame mode,
the LSB bit turns to Hi-impedance at the faster edge of ether FS falling edge or 9
th
rising edge of BCLK.
- PCM data input (DR)
DR is an input signal of 64Kbps PCM u/A-law data. The data is clocked by BCLK at the falling edge and fed into the D/A
block.
2-2-1-b LONG FRAME( LF ) / SHORT FRAME ( SF ) Automatic selection
AK2307/LV monitors the duration of the “H” level of FS and automatically selects LF or SF interface format.
period of FS=”H”
Interface format
MS0190-E-05
2005/12
11
more than 2 clocks of BCK
LF
1 clock of BCK
SF
2-2-1-c Frame format of the interface
Long Frame format
F S
D X
D R
B C L K
D on’t
D o n’t care
7
6
5
4
1
0
3
2
7
6
5
4
1
0
3
2
1 25 us(8K H z)
Short Frame format
FS
DX
DR
BCLK
Don’t
Don’t care
7
6
5
4
1
0
3
2
7
6
5
4
1
0
3
2
125us(8KHz)
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