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參數(shù)資料
| 型號： | AK2301A |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | Codec |
| 英文描述： | 3.3V Single channel PCM CODEC LSI |
| 中文描述： | 3.3單聲道的PCM CODEC芯片 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 158K |
| 代理商： | AK2301A |
ASAHI KASEI
AK2301A
PIN FUNCTION
Pin types
NIN:
Normal input
TOUT: Try state output
AIN:
Analog input
AOUT: Analog output
Pin# Name
Type
15
VFTN
Diffelential or single amplifire is composed with the VFTP and the external
registers. Transmit gain is defined by the ratio of the external registers.
16
VFTP
AIN
Positive analog input of the transmit OP amp.
14
GST
AOUT
Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTP.
7
GSR
AOUT
Output of the receive OP amp.
Receive gain is defined by the ratio of the external registers.
The differential output can be composed with using the VR.
8
VFR
AIN
Negative analog input of the receive OP amp.
9
VR
AOUT
Analog output of the D/A convertor equivalent to the received PCM code.
6
VDD
PWR
Positive supply voltage
+3.3V supply
19
VSS
PWR
Ground (0V)
5
FS
NIN
Frame sync input
This clock is input for the internal PLL which gerenates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK and do not stop
feeding.
3
BCLK
NIN
Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
The frequency of BCLK should be 256kHz or 512kHz and do not stop feeding.
2
DX
TOUT
Serial output of PCM data
The PCM data is synchronized with BCLK. This output remains in the high
impedance except for the period in which PCM data is transmitted.
4
DR
NIN
Serial input of PCM data
The PCM data is synchronized with BCLK.
23
MUTEN
NIN
Mute setting pin
“L” level forces both A/D, D/A output to mute state.
22
RSTN
NIN
Reset signal input pin
Reset operation starts by low input. This pin is used for the initialization at the
power up. Please use MUTEN pin together to avoid the popping sound output
until the LSI finish the initialaization after the power up.
（
Refer to P.13
）
18
VREF
AOUT
Analog ground output
External capacitance (1.0
μ
F or more) should be connected between this pin and
VSS.
Please do not connect external load to this pin.
20
PLLC
AOUT
PLL loop filter output
External capacitance (0.33
μ
F
±
40%: Includes temperature characteristic) should
be connected between this pin and VSS.
17
TAGND
AOUT
Analog ground output for transmitte OP amp
150uA load max.
External capacitance (1.0
μ
F or more) should be connected
between this pin and VSS. This pin is used as an analog ground for transmit OP
amp (AMPT).
11
12
AMP2I
13
10
AMP2O
21
24
1
TEAT3
<MS0300-E-00>
4
2004/3
PWR: Power / Ground
Function
AIN
Neagative analog input of the transmit OP amp.
AMP1I
AIN
Negative input of the universal OP amp
AMP1O
AOUT
Output of the universal OP amp
TEST1
TEST2
NIN
Test pins
（
”H”=test mode
）
Please tie to VSS
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