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參數(shù)資料
| 型號(hào)： | AK2048D |
| 廠商： | Asahi Kasei Microsystems Co.,Ltd |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:8; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:12; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:12-8 RoHS Compliant: No |
| 中文描述： | 200萬母語收發(fā)器 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 88K |
| 代理商： | AK2048D |
ASAHI K ASEI [AK 2048]
MS0073-E-00 2001/01
4
PIN DESCRIPTIONS
Pin Name
I/O
Function
RDATA
O
Receive Data output recovered from the incoming data. Delay time from the incoming
data to the RDATA is about 1.25bit. Output on the rising edge of RCLK .
Receive Clock Output recovered from the incoming data.
RCLK
O
RCRV
O
CRV (Code Rule Violation) output pin.
When AK 2048D detects the CRV of CMI codes from in the coming data, RCRV goes
to “high” synchronized with the violation data. CRV is detected for both “0” data and
“1” data. Refer to Fig.6, 11
Transmit Data Input pin.
Input on the falling edge of TCLK .
Transmit Clock Input pin.
If this input is “high”, AK 2048D generates CRV in the transmit data.
CRV is generated for both “0”data and “1”data. “High” input TCRV is accepted until 5
clocks duration. If the duration of “High” input is longer than 6 clocks, TCRV input
after 6th clock is ignored. Refer to Fig.4, 11
Test pin. Should be floated.
TDATA
I
TCLK
I
TCRV
I
TE ST1
NC
TE ST2
NC
Test pin. Should be floated.
LOCK
O
LOCK indicates the PLL status whether PLL is in the LOCK status or PLL is in the
UNLOCK status.
LOCK status
LOCK becomes “Low” when the sampled RCLK are all “Low” during the consecutive
32 RXA-RXB sample clock duration.
UN LOCK status
LOCK becomes “High” when the following both conditions are satisfied.
-
The sampled RCLK are “High” more than 5 clocks in the frame of the consecutive
256 RXA-RXB clock duration.
-
And the above happens in the 5 consecutive frames.
In another condition, LOCK keeps the current output status without change.
The output timing of this signal is asynchronous with RCLK .
When RST is “Low”, LOCK is fixed to “High”.
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