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參數(shù)資料
| 型號： | AIC809N23CUTR |
| 廠商： | Analog Integrations Corporation |
| 元件分類： | 復(fù)位半導(dǎo)體 |
| 英文描述： | 3-PIN MICROPROCESSOR RESET CIRCUITS |
| 中文描述： | 3引腳微處理器復(fù)位電路 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大小： | 414K |
| 代理商： | AIC809N23CUTR |
AIC809/AIC810
PIN DESCRIPTIONS
GND Pin
RESET
Pin (AIC809) : Active low output pin.
RESET
Output remains low while Vcc is below the reset
threshold.
RESET Pin (AIC810)
: Active high output pin. RESET output remains high while Vcc is below the reset
threshold.
Vcc Pin
: Supply voltage.
DETAIL DESCRIPTIONS OF TECHNICAL TERMS
7
: Ground.
RESET OUTPUT
μ
P will be activated at a valid reset state. These
μ
P supervisory circuits assert reset to prevent
code
execution
errors
power-down, or brownout conditions.
RESET
is guaranteed to be a logic low for
V
TH
>VCC>0.9V. Once VCC exceeds the reset
threshold, an internal timer keeps
RESET
low
for the reset timeout period; after this interval,
RESET
goes high.
If a brownout condition occurs (VCC drops below
the reset threshold),
RESET
goes low. Any time
VCC goes below the reset threshold, the internal
timer resets to zero, and
RESET
goes low. The
during
power-up,
internal timer is activated after VCC returns
above the reset threshold, and
RESET
remains
low for the reset timeout period.
BENEFITS OF HIGHLY ACCURATE RESET
THRESHOLD
AIC809/810 with specified voltage as 5V
±
10% or
3V
±
10% are ideal for systems using a 5V
±
5% or
3V
±
5% power supply. The reset is guaranteed to
assert after the power supply falls out of regulation,
but before power drops below the minimum
specified operating voltage range of the system
ICs. The pre-trimmed thresholds are reducing the
range over which an undesirable reset may occur.
APPLICATION INFORMATION
NEGATIVE-GOING VCC TRANSIENTS
In addition to issuing a reset to the
μ
P during
power-up, power-down, and brownout conditions,
AIC809
series
are
relatively
short-duration negative-going VCC transient.
resistant
to
ENSURING A VALID RESET OUTPUT DOWN
TO VCC=0
When VCC falls below 0.9V, AIC809
RESET
output no longer sinks current; it becomes an
open circuit. In this case, high-impedance CMOS
logic inputs connecting to
RESET
can drift to
undetermined voltages. Therefore, AIC809/810
with CMOS is perfect for most applications of VCC
below 0.9V. However in applications where
RESET
must be valid down to 0V, adding a
pull-down resistor to
RESET
causes any leakage
currents to flow to ground, holding
RESET
low.
INTERFACING TO
μ
P WITH BIDIRECTIONAL
RESET PINS
The
RESET
output on the AIC809N is open drain,
this device interfaces easily with
μ
Ps that have
bidirectional reset pins. Connecting the
μ
P
supervisor’s
RESET
output directly to the
microcontroller’s
RESET
pin with a single pull-up
resistor allows either device to assert reset.
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