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參數(shù)資料
| 型號(hào)： | AGM2416B |
| 廠商： | AZ Displays, Inc. |
| 英文描述： | SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY |
| 中文描述： | 規(guī)格液晶顯示器 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 1006K |
| 代理商： | AGM2416B |
AGM2412B
Page 4 of 12
AZ DISPLAYS, INC.
20
21
22
V34R
V12R
V0R
Normally use the bias voltages set by a resistor divider
Ensure that voltages are set such that V
SS
V
5
< V
43
< V
12
< V
0
.
V
iL
and V
iR
(i = 0,12, 43, 5) must connect to an external power supply, and
supply regular voltage which is assigned by specification for each power pin
Common Pin
Pin No.
23
24
25
Symbol
V0L
V12L
Function Description
V34L
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that V
SS
< V
43
< V
12
< V
0
.
V
iL
and V
iR
(i = 0,12, 43) must connect to an external power supply, and
supply regular voltage that is assigned by specification for each power pin.
26
27
28
29
30
31
32
33
34
VSS
VSS
VSS
VDD
VDD
VDD
EIO2
D7
Ground
Logic power supply
Shift data input for shift register at common mode
Dual mode data input at common mode
Control input pin for output of non-select level
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
When set to V
SS
level "L", the LCD drive output pins (Y
1
-Y
160
) are set to level
Vss.
When set to "L±, the contents of the shift register are reset to not reading
data. When the /DISPOFF function is canceled, the driver outputs non-select
level (V
12
or V
43
), and the shift data is read at the next falling edge of the LP. At
that time, if /DISPOFF removal time does not correspond to what is shown in
AC characteristics, the shift data is not read correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Shift clock pulse input pin for bi-directional shift register
* Data is shifted at the falling edge of the clock pulse.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage
level, and controls the LCD drive circuit.
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the shift
register output signal and the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Bias power supply pins for LCD drive voltage
Normally use the bias voltages set by a resistor divider.
Ensure that voltages are set such that V
SS
< V
43
< V
12
< V
0
.
V
iL
and V
iR
(i = 0,12, 43) must connect to an external power supply, and
supply regular voltage that is assigned by specification for each power pin.
DOFFB
35
LP
36
FR
37
38
39
V34R
V12R
V0R
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