Revision 16 2-77 1.2 V DC Core Voltage Table 2-97 FIFO Worst Commercial-Case Conditions:" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLP125V2-CS281
寤�(ch菐ng)鍟嗭細 Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 126/134闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA IGLOO PLUS 125K 281-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 184
绯诲垪锛� IGLOO PLUS
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3120
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 212
闁€(m茅n)鏁�(sh霉)锛� 125000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 281-TFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 281-CSP锛�10x10锛�
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IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-77
1.2 V DC Core Voltage
Table 2-97 FIFO
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.14 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
3.44
ns
tENH
REN, WEN Hold Time
0.26
ns
tBKS
BLK Setup Time
0.30
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
1.30
ns
tDH
Input Data (WD) Hold Time
0.41
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
5.67
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
3.02
ns
tRCKEF
RCLK High to Empty Flag Valid
6.02
ns
tWCKFF
WCLK High to Full Flag Valid
5.71
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
22.17
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
5.93
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
21.94
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
3.41
ns
RESET Low to Data Out Low on RD (pipelined)
3.41
ns
tREMRSTB
RESET Removal
1.02
ns
tRECRSTB
RESET Recovery
5.48
ns
tMPWRSTB
RESET Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency for FIFO
92
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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AGLP125V2-CS281I 鍔熻兘鎻忚堪:IC FPGA IGLOO PLUS 125K 281-CSP RoHS:鍚� 椤�(l猫i)鍒�:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO PLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:90 绯诲垪:ProASIC3 LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):36864 杓稿叆/杓稿嚭鏁�(sh霉):157 闁€(m茅n)鏁�(sh霉):250000 闆绘簮闆诲:1.425 V ~ 1.575 V 瀹夎椤�(l猫i)鍨�:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 125°C 灏佽/澶栨:256-LBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:256-FPBGA锛�17x17锛�
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