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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLP060V5-CSG289I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 90/134闋�(y猫)
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鎻忚堪锛� IC FPGA IGLOO PLUS 60K 289-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 152
绯诲垪锛� IGLOO PLUS
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1584
RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 157
闁€(m茅n)鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 289-TFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 289-CSP锛�14x14锛�
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IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-45
Input Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-14 Input Register Timing Diagram
50%
Clear
Out_1
CLK
Data
Preset
50%
t
ISUD
t
IHD
50%
t
ICLKQ
1
0
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH tICKMPWL
50%
Table 2-74 Input Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tICLKQ
Clock-to-Q of the Input Data Register
0.41
ns
tISUD
Data Setup Time for the Input Data Register
0.32
ns
tIHD
Data Hold Time for the Input Data Register
0.00
ns
tICLR2Q
Asynchronous Clear-to-Q of the Input Data Register
0.57
ns
tIPRE2Q
Asynchronous Preset-to-Q of the Input Data Register
0.57
ns
tIREMCLR
Asynchronous Clear Removal Time for the Input Data Register
0.00
ns
tIRECCLR
Asynchronous Clear Recovery Time for the Input Data Register
0.24
ns
tIREMPRE
Asynchronous Preset Removal Time for the Input Data Register
0.00
ns
tIRECPRE
Asynchronous Preset Recovery Time for the Input Data Register
0.24
ns
tIWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register
0.19
ns
tIWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register
0.19
ns
tICKMPWH
Clock Minimum Pulse Width High for the Input Data Register
0.31
ns
tICKMPWL
Clock Minimum Pulse Width Low for the Input Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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