2-56 Revision 16 1.2 V DC Core Voltage Table 2-83 Register Delays Commercial-" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLP060V5-CS201I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 103/134闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA IGLOO PLUS 60K 201-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 384
绯诲垪锛� IGLOO PLUS
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RAM 浣嶇附瑷�(j矛)锛� 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 157
闁€(m茅n)鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤�(l猫i)鍨嬶細 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 201-VFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 201-CSP锛�8x8锛�
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IGLOO PLUS DC and Switching Characteristics
2-56
Revision 16
1.2 V DC Core Voltage
Table 2-83 Register Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
1.61
ns
tSUD
Data Setup Time for the Core Register
1.17
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
1.29
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.87
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.89
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.24
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.24
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.46
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.46
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.95
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.95
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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AGLP060-V5CS289I 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū(ch膿ng):Actel Corporation 鍔熻兘鎻忚堪:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology
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