Revision 16 2-77 1.2 V DC Core Voltage Table 2-97 FIFO Worst Commercial-Case Conditions:" />
參數(shù)資料
型號: AGLP060V2-CSG289I
廠商: Microsemi SoC
文件頁數(shù): 126/134頁
文件大小: 0K
描述: IC FPGA IGLOO PLUS 60K 289-CSP
標準包裝: 152
系列: IGLOO PLUS
邏輯元件/單元數(shù): 1584
RAM 位總計: 18432
輸入/輸出數(shù): 157
門數(shù): 60000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 289-TFBGA,CSBGA
供應商設備封裝: 289-CSP(14x14)
IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-77
1.2 V DC Core Voltage
Table 2-97 FIFO
Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V
Parameter
Description
Std.
Units
tENS
REN, WEN Setup Time
3.44
ns
tENH
REN, WEN Hold Time
0.26
ns
tBKS
BLK Setup Time
0.30
ns
tBKH
BLK Hold Time
0.00
ns
tDS
Input Data (WD) Setup Time
1.30
ns
tDH
Input Data (WD) Hold Time
0.41
ns
tCKQ1
Clock High to New Data Valid on RD (flow-through)
5.67
ns
tCKQ2
Clock High to New Data Valid on RD (pipelined)
3.02
ns
tRCKEF
RCLK High to Empty Flag Valid
6.02
ns
tWCKFF
WCLK High to Full Flag Valid
5.71
ns
tCKAF
Clock High to Almost Empty/Full Flag Valid
22.17
ns
tRSTFG
RESET Low to Empty/Full Flag Valid
5.93
ns
tRSTAF
RESET Low to Almost Empty/Full Flag Valid
21.94
ns
tRSTBQ
RESET Low to Data Out Low on RD (flow-through)
3.41
ns
RESET Low to Data Out Low on RD (pipelined)
3.41
ns
tREMRSTB
RESET Removal
1.02
ns
tRECRSTB
RESET Recovery
5.48
ns
tMPWRSTB
RESET Minimum Pulse Width
1.18
ns
tCYC
Clock Cycle Time
10.90
ns
FMAX
Maximum Frequency for FIFO
92
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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