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參數(shù)資料
| 型號： | AGLP030V5-VQ128I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 33/134頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA IGLOO PLUS 30K 128-VQFN |
| 標準包裝： | 90 |
| 系列： | IGLOO PLUS |
| 邏輯元件/單元數(shù)： | 792 |
| 輸入/輸出數(shù)： | 101 |
| 門數(shù)： | 30000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 128-TQFP |
| 供應商設備封裝： | 128-VTQFP（14x14） |
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Datasheet Information
5-2
Revision 16
Revision 12
(continued)
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to t
he "Spine Architecture"
section of the Global Resources chapter in the IGLOO PLUS FPGA Fabric
User's Guide (SAR 34733).
(example) (SAR 37107).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34887).
Minimum pulse width High and Low values were added to the tables in the "Global
Tree Timing Characteristics" section. The maximum frequency for global clock
parameter was removed from these tables because a frequency on the global is only
an indication of what the global network can do. There are other limiters such as the
SRAM, I/Os, and PLL. SmartTime software should be used to determine the design
frequency (SAR 36963).
CCC/PLL Specification were updated. A note was added to both tables indicating
that when the CCC/PLL core is generated by Microsemi core generator software, not
all delay values of the specified delay increments are available (SAR 34820).
The value for serial clock was missing from these tables and has been restored. The
value and units for input cycle-to-cycle jitter were incorrect and have been restored.
The note to Table 2-90 IGLOO PLUS CCC/PLL Specification giving specifications
for which measurements done was corrected from VCC/VCCPLL = 1.14 V to
VCC/VCCPLL = 1.425 V. The Delay Range in Block: Programmable Delay 2 value in
Table 2-91 IGLOO PLUS CCC/PLL Specification was corrected from 0.025 to 0.863
(SAR 37058).
Figure 2-28 Write Access after Read onto Same Address was deleted. Reference
was made to a new application note, Simultaneous Read-Write Operations in Dual-
Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in detail
(SAR 34868).
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-32 FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35748).
The "Pin Descriptions and Packaging" chapter has been added (SAR 34769).
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 34769).
Revision 11
(July 2010)
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "IGLOO
PLUS Device Status" table indicates the status for each device in the family.
N/A
The "Reprogrammable Flash Technology" section was revised to add "250 MHz
(1.5 V systems) and 160 MHz (1.2 V systems) System Performance."
The "I/Os with Advanced I/O Standards" section was revised to add definitions for
hot-swap and cold-sparing.
Conditional statements regarding hot insertion were removed from the description of
VI in Table 2-1 Absolute Maximum Ratings, since all IGLOO PLUS devices are hot
insertion enabled.
Revision
Changes
Page
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相關代理商/技術參數(shù) |
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| AGLP030-V5VQ289 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V5VQ289ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V5VQ289I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030-V5VQ289PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO PLUS Low-Power Flash FPGAs with FlashFreeze Technology |
| AGLP030V5-VQG128 | 功能描述:IC FPGA IGLOO PLUS 30K 128-VQFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:IGLOO PLUS 標準包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應商設備封裝:289-CSP（14x14） |
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