2-68 Revision 16 Timing Characteristics 1.5 V DC Core Voltage Table 2-92 RAM4K9
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLP030V5-CSG201
寤犲晢锛� Microsemi SoC
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鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA IGLOO PLUS 30K 201-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 384
绯诲垪锛� IGLOO PLUS
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 792
杓稿叆/杓稿嚭鏁�(sh霉)锛� 120
闁€鏁�(sh霉)锛� 30000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 201-VFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 201-CSP锛�8x8锛�
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IGLOO PLUS DC and Switching Characteristics
2-68
Revision 16
Timing Characteristics
1.5 V DC Core Voltage
Table 2-92 RAM4K9
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.69
ns
tAH
Address hold time
0.13
ns
tENS
REN, WEN setup time
0.68
ns
tENH
REN, WEN hold time
0.13
ns
tBKS
BLK setup time
1.37
ns
tBKH
BLK hold time
0.13
ns
tDS
Input data (DIN) setup time
0.59
ns
tDH
Input data (DIN) hold time
0.30
ns
tCKQ1
Clock High to new data valid on DOUT (output retained, WMODE = 0)
2.94
ns
Clock High to new data valid on DOUT (flow-through, WMODE = 1)
2.55
ns
tCKQ2
Clock High to new data valid on DOUT (pipelined)
1.51
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same address 鈥� applicable
to closing edge
0.29
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address 鈥�
applicable to opening edge
0.24
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address 鈥�
applicable to opening edge
0.40
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
1.72
ns
RESET Low to data out Low on DOUT (pipelined)
1.72
ns
tREMRSTB
RESET removal
0.51
ns
tRECRSTB
RESET recovery
2.68
ns
tMPWRSTB RESET minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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AGLP030V5-CSG289 鍔熻兘鎻忚堪:IC FPGA IGLOO PLUS 30K 289-CSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOO PLUS 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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