Revision 16 2-79 JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG t" />
參數(shù)資料
型號: AGLP030V2-CSG289I
廠商: Microsemi SoC
文件頁數(shù): 128/134頁
文件大?。?/td> 0K
描述: IC FPGA IGLOO PLUS 30K 289-CSP
標準包裝: 152
系列: IGLOO PLUS
邏輯元件/單元數(shù): 792
輸入/輸出數(shù): 120
門數(shù): 30000
電源電壓: 1.14 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 289-TFBGA,CSBGA
供應商設備封裝: 289-CSP(14x14)
IGLOO PLUS Low Power Flash FPGAs
Revision 16
2-79
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-100 JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
Std.
Units
tDISU
Test Data Input Setup Time
1.00
ns
tDIHD
Test Data Input Hold Time
2.00
ns
tTMSSU
Test Mode Select Setup Time
1.00
ns
tTMDHD
Test Mode Select Hold Time
2.00
ns
tTCK2Q
Clock to Q (data out)
8.00
ns
tRSTB2Q
Reset to Q (data out)
25.00
ns
FTCKMAX
TCK Maximum Frequency
15
MHz
tTRSTREM
ResetB Removal Time
0.58
ns
tTRSTREC
ResetB Recovery Time
0.00
ns
tTRSTMPW
ResetB Minimum Pulse
TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-101 JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tDISU
Test Data Input Setup Time
1.50
ns
tDIHD
Test Data Input Hold Time
3.00
ns
tTMSSU
Test Mode Select Setup Time
1.50
ns
tTMDHD
Test Mode Select Hold Time
3.00
ns
tTCK2Q
Clock to Q (data out)
11.00
ns
tRSTB2Q
Reset to Q (data out)
30.00
ns
FTCKMAX
TCK Maximum Frequency
9.00
MHz
tTRSTREM
ResetB Removal Time
1.18
ns
tTRSTREC
ResetB Recovery Time
0.00
ns
tTRSTMPW
ResetB Minimum Pulse
TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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