2-80 Revision 17 Table 2-105 RAM512X18 Commercial-Case Conditions: T
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鎻忚堪锛� IC FPGA NANO 1KB 250K 100VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO nano
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IGLOO nano DC and Switching Characteristics
2-80
Revision 17
Table 2-105 RAM512X18
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std. Units
tAS
Address setup time
1.28
ns
tAH
Address hold time
0.25
ns
tENS
REN, WEN setup time
1.13
ns
tENH
REN, WEN hold time
0.13
ns
tDS
Input data (WD) setup time
1.10
ns
tDH
Input data (WD) hold time
0.55
ns
tCKQ1
Clock High to new data valid on RD (output retained)
6.56
ns
tCKQ2
Clock High to new data valid on RD (pipelined)
2.67
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address;
applicable to opening edge
0.87
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address;
applicable to opening edge
1.04
ns
tRSTBQ
RESET LOW to data out LOW on RD (flow through)
3.21
ns
RESET LOW to data out LOW on RD (pipelined)
3.21
ns
tREMRSTB
RESET removal
0.93
ns
tRECRSTB
RESET recovery
4.94
ns
tMPWRSTB RESET minimum pulse width
1.18
ns
tCYC
Clock cycle time
10.90
ns
FMAX
Maximum frequency
92
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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