Revision 17 2-77 Timing Characteristics 1.5 V DC Core Voltage Table 2-102 RAM4K9
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLN250V2-VQG100I
寤犲晢锛� Microsemi SoC
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妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 6144
RAM 浣嶇附瑷�(j矛)锛� 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 68
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
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宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-77
Timing Characteristics
1.5 V DC Core Voltage
Table 2-102 RAM4K9
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tAS
Address setup time
0.69
ns
tAH
Address hold time
0.13
ns
tENS
REN, WEN setup time
0.68
ns
tENH
REN, WEN hold time
0.13
ns
tBKS
BLK setup time
1.37
ns
tBKH
BLK hold time
0.13
ns
tDS
Input data (DIN) setup time
0.59
ns
tDH
Input data (DIN) hold time
0.30
ns
tCKQ1
Clock HIGH to new data valid on DOUT (output retained, WMODE = 0)
2.94
ns
Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1)
2.55
ns
tCKQ2
Clock HIGH to new data valid on DOUT (pipelined)
1.51
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same address; applicable
to closing edge
0.23
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address;
applicable to opening edge
0.35
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address;
applicable to opening edge
0.41
ns
tRSTBQ
RESET Low to data out Low on DOUT (flow-through)
1.72
ns
RESET Low to data out Low on DOUT (pipelined)
1.72
ns
tREMRSTB
RESET removal
0.51
ns
tRECRSTB
RESET recovery
2.68
ns
tMPWRSTB RESET minimum pulse width
0.68
ns
tCYC
Clock cycle time
6.24
ns
FMAX
Maximum frequency
160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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