Revision 17 5-7 Revision 1 (cont鈥檇) The "QN48" pin diagram was revised. 4-16 Packaging Advance v0.2
鍙冩暩璩囨枡
鍨嬭櫉锛� AGLN250V2-VQ100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩锛� 54/150闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 250K 100VQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁革細 6144
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁革細 68
闁€鏁革細 250000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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IGLOO nano Low Power Flash FPGAs
Revision 17
5-7
Revision 1 (cont鈥檇)
The "QN48" pin diagram was revised.
Packaging Advance
v0.2
Note 2 for the "QN48", "QN68", and "100-Pin QFN" pin diagrams was changed to
"The die attach paddle of the package is tied to ground (GND)."
The "VQ100" pin diagram was revised to move the pin IDs to the upper left corner
instead of the upper right corner.
Revision 0 (Oct 2008)
Product Brief Advance
v0.2
The following tables and sections were updated to add the UC81 and CS81
packages for AGL030:
N/A
The "I/Os Per Package" table was updated to add the following information to
table note 4: "For nano devices, the VQ100 package is offered in both leaded and
RoHS-compliant versions. All other packages are RoHS-compliant only."
updated to remove QN100 for AGLN250.
The device architecture figures, Figure 1-3 IGLOO Device Architecture Overview
through
The "PLL and CCC" section was revised to include information about CCC-GLs in
AGLN020 and smaller devices.
The "I/Os with Advanced I/O Standards" section was revised to add information
about IGLOO nano devices supporting double-data-rate applications.
Revision / Version
Changes
Page
鐩搁棞PDF璩囨枡
PDF鎻忚堪
AGLN250V2-ZVQ100I IC FPGA NANO 1KB 250K 100VQFP
EP1K10QC208-1N IC ACEX 1K FPGA 10K 208-PQFP
EP1K10QC208-1 IC ACEX 1K FPGA 10K 208-PQFP
BR25S256FJ-WE2 IC EEPROM SPI 256KB 20MHZ 8-SOP
EP4CE10F17C9LN IC CYCLONE IV FPGA 10K 256FBGA
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