Revision 17 2-29 3.3 V LVCMOS Wide Range Table 2-40 Minimum and Maximum DC Input and Output Levels" />
參數(shù)資料
型號: AGLN125V5-ZVQG100
廠商: Microsemi SoC
文件頁數(shù): 91/150頁
文件大?。?/td> 0K
描述: IC FPGA NANO 1KB 125K 100VQFP
標準包裝: 90
系列: IGLOO nano
邏輯元件/單元數(shù): 3072
RAM 位總計: 36864
輸入/輸出數(shù): 71
門數(shù): 125000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -20°C ~ 70°C
封裝/外殼: 100-TQFP
供應商設備封裝: 100-VQFP(14x14)
IGLOO nano Low Power Flash FPGAs
Revision 17
2-29
3.3 V LVCMOS Wide Range
Table 2-40 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
3.3 V LVCMOS
Wide Range1
Equivalent
Software
Default
Drive
Strength
Option4
VIL
VIH
VOL
VOH
IOL
IOH IIL 2 IIH 3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VA
A
A5
100 A
2 mA
–0.3
0.8
2
3.6
0.2
VCCI – 0.2 100
100
10
100 A
4 mA
–0.3
0.8
2
3.6
0.2
VCCI – 0.2 100
100
10
100 A
6 mA
–0.3
0.8
2
3.6
0.2
VCCI – 0.2 100
100
10
100 A
8mA
–0.3
0.8
2
3.6
0.2
VCCI – 0.2 100
100
10
Notes:
1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B
specification.
2. IIL is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
4. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
5. Currents are measured at 85°C junction temperature.
6. Software default selection is highlighted in gray.
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