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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLN125V5-CSG81I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 6/150闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 125K 81-CSP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 640
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 3072
RAM 浣嶇附瑷�(j矛)锛� 36864
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闁€鏁�(sh霉)锛� 125000
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灏佽/澶栨锛� 81-WFBGA锛孋SBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 81-CSP锛�5x5锛�
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-87
Embedded FlashROM Characteristics
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Figure 2-41 Timing Diagram
A0
A1
tSU
tHOLD
tSU
tHOLD
tSU
tHOLD
tCKQ2
CLK
Address
Data
D0
D1
Table 2-108 Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
Std.
Units
tSU
Address Setup Time
0.57
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
20.90
ns
FMAX
Maximum Clock Frequency
15
MHz
Table 2-109 Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.14 V
Parameter
Description
Std.
Units
tSU
Address Setup Time
0.59
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
35.74
ns
FMAX
Maximum Clock Frequency
10
MHz
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