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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AGLN060V5-ZVQG100 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋佹暩(sh霉)锛� | 6/150闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC FPGA NANO 1KB 60K 100VQFP |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 90 |
| 绯诲垪锛� | IGLOO nano |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 1536 |
| RAM 浣嶇附瑷�(j矛)锛� | 18432 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 71 |
| 闁€鏁�(sh霉)锛� | 60000 |
| 闆绘簮闆诲锛� | 1.425 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -20°C ~ 70°C |
| 灏佽/澶栨锛� | 100-TQFP |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 100-VQFP锛�14x14锛� |
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-87
Embedded FlashROM Characteristics
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Figure 2-41 Timing Diagram
A0
A1
tSU
tHOLD
tSU
tHOLD
tSU
tHOLD
tCKQ2
CLK
Address
Data
D0
D1
Table 2-108 Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.425 V
Parameter
Description
Std.
Units
tSU
Address Setup Time
0.57
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
20.90
ns
FMAX
Maximum Clock Frequency
15
MHz
Table 2-109 Embedded FlashROM Access Time
Worst Commercial-Case Conditions: TJ = 70掳C, VCC = 1.14 V
Parameter
Description
Std.
Units
tSU
Address Setup Time
0.59
ns
tHOLD
Address Hold Time
0.00
ns
tCK2Q
Clock to Out
35.74
ns
FMAX
Maximum Clock Frequency
10
MHz
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| A3P060-VQ100 | IC FPGA 1KB FLASH 60K 100-VQFP |
| AGL060V5-VQ100 | IC FPGA 1KB FLASH 60K 100-VQFP |
| AGLN060V5-ZVQ100 | IC FPGA NANO 1KB 60K 100VQFP |
| AYM28DTAT-S189 | CONN EDGECARD 56POS R/A .156 SLD |
| ASM28DTAT-S189 | CONN EDGECARD 56POS R/A .156 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AGLN060V5-ZVQG100I | 鍔熻兘鎻忚堪:IC FPGA NANO 1KB 60K 100VQFP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:IGLOO nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛� |
| AGLN125V2-CSG81 | 鍔熻兘鎻忚堪:IC FPGA NANO 1KB 125K 81-CSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:IGLOO nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛� |
| AGLN125V2-CSG81I | 鍔熻兘鎻忚堪:IC FPGA NANO 1KB 125K 81-CSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:IGLOO nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛� |
| AGLN125V2-CSG81Y | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:Res Thick Film NET 2K Ohm 5% 7/20W 卤300ppm/掳C ISOL Ceramic 14-Pin Flat Flat SMD Tube |
| AGLN125V2-DIELOT | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:AGLN125V2-DIELOT - Gel-pak, waffle pack, wafer, diced wafer on film |
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