Revision 17 2-29 3.3 V LVCMOS Wide Range Table 2-40 Minimum and Maximum DC Input and Output Levels" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLN030V5-ZQNG48
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 91/150闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 30K 48-QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 260
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 34
闁€(m茅n)鏁�(sh霉)锛� 30000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -20°C ~ 70°C
灏佽/澶栨锛� 48-VFQFN 瑁搁湶鐒婄洡(p谩n)
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 48-QFN锛�6x6锛�
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-29
3.3 V LVCMOS Wide Range
Table 2-40 Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
3.3 V LVCMOS
Wide Range1
Equivalent
Software
Default
Drive
Strength
Option4
VIL
VIH
VOL
VOH
IOL
IOH IIL 2 IIH 3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VA
A
A5
100 A
2 mA
鈥�0.3
0.8
2
3.6
0.2
VCCI 鈥� 0.2 100
100
10
100 A
4 mA
鈥�0.3
0.8
2
3.6
0.2
VCCI 鈥� 0.2 100
100
10
100 A
6 mA
鈥�0.3
0.8
2
3.6
0.2
VCCI 鈥� 0.2 100
100
10
100 A
8mA
鈥�0.3
0.8
2
3.6
0.2
VCCI 鈥� 0.2 100
100
10
Notes:
1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B
specification.
2. IIL is the input leakage current per I/O pin over recommended operating conditions where 鈥�0.3 < VIN < VIL.
3. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
4. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤100 A. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
5. Currents are measured at 85掳C junction temperature.
6. Software default selection is highlighted in gray.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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AGLN030V5-ZQNG48I 鍔熻兘鎻忚堪:IC FPGA NANO 1KB 30K 48-QFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
AGLN030V5-ZQNG68 鍔熻兘鎻忚堪:IC FPGA NANO 1KB 30K 68-QFN RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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AGLN030V5-ZUCG81 鍔熻兘鎻忚堪:IC FPGA NANO 1KB 30K 81-UCSP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸(m茅n)闄e垪锛� 绯诲垪:IGLOO nano 妯�(bi膩o)婧�(zh菙n)鍖呰:152 绯诲垪:IGLOO PLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):792 RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):120 闁€(m茅n)鏁�(sh霉):30000 闆绘簮闆诲:1.14 V ~ 1.575 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:-40°C ~ 85°C 灏佽/澶栨:289-TFBGA锛孋SBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:289-CSP锛�14x14锛�
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