2-54 Revision 17 Output DDR Module Figure 2-19 Output DDR Timing Model Table 2-81 <" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AGLN030V2-ZVQG100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 119/150闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 30K 100VQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 77
闁€(m茅n)鏁�(sh霉)锛� 30000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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IGLOO nano DC and Switching Characteristics
2-54
Revision 17
Output DDR Module
Figure 2-19 Output DDR Timing Model
Table 2-81 Parameter Definitions
Parameter Name
Parameter Definition
Measuring Nodes (from, to)
tDDROCLKQ
Clock-to-Out
B, E
tDDROCLR2Q
Asynchronous Clear-to-Out
C, E
tDDROREMCLR
Clear Removal
C, B
tDDRORECCLR
Clear Recovery
C, B
tDDROSUD1
Data Setup Data_F
A, B
tDDROSUD2
Data Setup Data_R
D, B
tDDROHD1
Data Hold Data_F
A, B
tDDROHD2
Data Hold Data_R
D, B
Data_F
(from core)
CLK
CLKBUF
Out
FF2
INBUF
CLR
DDR_OUT
Output DDR
FF1
0
1
X
A
B
D
E
C
B
OUTBUF
Data_R
(from core)
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
AGL030V2-VQG100I IC FPGA 1KB FLASH 30K 100-VQFP
AGLN030V2-ZVQ100I IC FPGA NANO 1KB 30K 100VQFP
HCC60DRYN-S734 CONN EDGECARD 120PS DIP .100 SLD
AT24C01BN-SH-B IC EEPROM 1KBIT 1MHZ 8SOIC
HCC60DRYH-S734 CONN EDGECARD 120PS DIP .100 SLD
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