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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGLN030V2-ZVQ100I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 146/150闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA NANO 1KB 30K 100VQFP
妯欐簴鍖呰锛� 90
绯诲垪锛� IGLOO nano
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 77
闁€鏁�(sh霉)锛� 30000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 100-TQFP
渚涙噳鍟嗚ō鍌欏皝瑁濓細 100-VQFP锛�14x14锛�
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IGLOO nano Low Power Flash FPGAs
Revision 17
2-79
1.2 V DC Core Voltage
Table 2-104 RAM4K9
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tAS
Address setup time
1.28
ns
tAH
Address hold time
0.25
ns
tENS
REN, WEN setup time
1.25
ns
tENH
REN, WEN hold time
0.25
ns
tBKS
BLK setup time
2.54
ns
tBKH
BLK hold time
0.25
ns
tDS
Input data (DIN) setup time
1.10
ns
tDH
Input data (DIN) hold time
0.55
ns
tCKQ1
Clock HIGH to new data valid on DOUT (output retained, WMODE = 0)
5.51
ns
Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1)
4.77
ns
tCKQ2
Clock HIGH to new data valid on DOUT (pipelined)
2.82
ns
tC2CWWL1
Address collision clk-to-clk delay for reliable write after write on same address;
applicable to closing edge
0.30
ns
tC2CRWH1
Address collision clk-to-clk delay for reliable read access after write on same address;
applicable to opening edge
0.89
ns
tC2CWRH1
Address collision clk-to-clk delay for reliable write access after read on same address;
applicable to opening edge
1.01
ns
tRSTBQ
RESET LOW to data out LOW on DOUT (flow-through)
3.21
ns
RESET LOW to data out LOW on DO (pipelined)
3.21
ns
tREMRSTB
RESET removal
0.93
ns
tRECRSTB
RESET recovery
4.94
ns
tMPWRSTB RESET minimum pulse width
1.18
ns
tCYC
Clock cycle time
10.90
ns
FMAX
Maximum frequency
92
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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