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IGLOO nano Low Power Flash FPGAs
Revision 17
2-53
1.2 V DC Core Voltage
Table 2-80 Input DDR Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tDDRICLKQ1
Clock-to-Out Out_QR for Input DDR
0.76
ns
tDDRICLKQ2
Clock-to-Out Out_QF for Input DDR
0.94
ns
tDDRISUD1
Data Setup for Input DDR (negedge)
0.93
ns
tDDRISUD2
Data Setup for Input DDR (posedge)
0.84
ns
tDDRIHD1
Data Hold for Input DDR (negedge)
0.00
ns
tDDRIHD2
Data Hold for Input DDR (posedge)
0.00
ns
tDDRICLR2Q1
Asynchronous Clear-to-Out Out_QR for Input DDR
1.23
ns
tDDRICLR2Q2
Asynchronous Clear-to-Out Out_QF for Input DDR
1.42
ns
tDDRIREMCLR
Asynchronous Clear Removal Time for Input DDR
0.00
ns
tDDRIRECCLR
Asynchronous Clear Recovery Time for Input DDR
0.24
ns
tDDRIWCLR
Asynchronous Clear Minimum Pulse Width for Input DDR
0.19
ns
tDDRICKMPWH
Clock Minimum Pulse Width HIGH for Input DDR
0.31
ns
tDDRICKMPWL
Clock Minimum Pulse Width LOW for Input DDR
0.28
ns
FDDRIMAX
Maximum Frequency for Input DDR
160.00
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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