2-18 Revision 23 Combinatorial Cells Contribution鈥擯C-CELL
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL600V2-FG484I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 179/250闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 600K 484-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 13824
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 235
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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IGLOO DC and Switching Characteristics
2-18
Revision 23
Combinatorial Cells Contribution鈥擯C-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-23 on
FCLK is the global clock signal frequency.
Routing Net Contribution鈥擯NET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs鈥攇uidelines are provided in Table 2-23 on
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution鈥擯INPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-23 on page 2-19.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution鈥擯OUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate鈥攇uidelines are provided in Table 2-23 on page 2-19.
1 is the I/O buffer enable rate鈥攇uidelines are provided in Table 2-24 on page 2-19.
FCLK is the global clock signal frequency.
RAM Contribution鈥擯MEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations鈥攇uidelines are provided in Table 2-24 on
PLL Contribution鈥擯PLL
PPLL = PDC4 + PAC13 *FCLKOUT
FCLKOUT is the output clock frequency.
If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
M1AGL600V2-FGG484I IC FPGA 1KB FLASH 600K 484-FBGA
FMC18DRYN-S93 CONN EDGECARD 36POS .100 DIP SLD
FMC18DRYH-S93 CONN EDGECARD 36POS .100 DIP SLD
FMC12DREI-S734 CONN EDGECARD 24POS .100 EYELET
ASC50DRTN-S13 CONN EDGECARD 100POS .100 EXTEND
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
AGL600V2-FGG144 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.2-1.5V 144FPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�(j矛):221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241
AGL600V2-FGG144I 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 600K 144-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�(j矛):- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
AGL600V2-FGG144T 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:AGL600V2-FGG144T - Trays
AGL600V2-FGG256 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.2-1.5V 256FPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�(j矛):221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241
AGL600V2-FGG256I 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.2-1.5V 256FPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�(j矛):221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241