Revision 23 2-41 Single-Ended I/O Characteristics 3.3 V LVTTL / 3.3 V LVCMOS Low-Voltage Transistor鈥揟ransistor " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL400V2-FG144
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 204/250闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 400K 144FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 9216
RAM 浣嶇附瑷堬細 55296
杓稿叆/杓稿嚭鏁�(sh霉)锛� 97
闁€鏁�(sh霉)锛� 400000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 144-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 144-FPBGA锛�13x13锛�
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IGLOO Low Power Flash FPGAs
Revision 23
2-41
Single-Ended I/O Characteristics
3.3 V LVTTL / 3.3 V LVCMOS
Low-Voltage Transistor鈥揟ransistor Logic (LVTTL) is a general-purpose standard (EIA/JESD) for 3.3 V
applications. It uses an LVTTL input buffer and push-pull output buffer. Furthermore, all LVCMOS 3.3 V
software macros comply with LVCMOS 3.3 V wide range as specified in the JESD8a specification.
Table 2-47 Minimum and Maximum DC Input and Output Levels
Applicable to Advanced I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
2
25
27
10 10
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
25
27
10 10
6 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
6
51
54
10 10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
51
54
10 10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12 12
103
109
10 10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16 16
132
127
10 10
24 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
24 24
268
181
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at 100掳C junction temperature and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
Table 2-48 Minimum and Maximum DC Input and Output Levels
Applicable to Standard Plus I/O Banks
3.3 V LVTTL /
3.3 V LVCMOS
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
2 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
2
25
27
10
4 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
4
25
27
10
6 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
6
51
54
10
8 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
8
51
54
10
12 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
12
103
109
10
16 mA
鈥�0.3
0.8
2
3.6
0.4
2.4
16
103
109
10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where 鈥�0.3 V < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
larger when operating outside recommended ranges
3. Currents are measured at 100掳C junction temperature and maximum voltage.
4. Currents are measured at 85掳C junction temperature.
5. Software default selection highlighted in gray.
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