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IGLOO DC and Switching Characteristics
2-32
Revision 23
Table 2-34 Summary of I/O Timing Characteristics鈥擲oftware Default Settings, Std. Speed Grade,
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V, Worst-Case VCCI (per
standard)
Applicable to Advanced I/O Banks
I/O
S
tan
dard
Dr
ive
S
trength
Eq
uivalen
tSo
ft
ware
Default
Drive
S
trength
Option
1
Slew
Rat
e
Ca
p
acitive
Lo
ad
(p
F)
Ex
te
rn
al
R
esi
st
or
(
)
t DO
UT
(ns)
t DP
(ns)
t DI
N
(ns)
t PY
(ns)
t EOUT
(ns)
t ZL
(ns)
t ZH
(ns)
t LZ
(ns)
t HZ
(ns)
t ZLS
(ns)
t ZH
S
(ns)
Unit
s
3.3 V
LVTTL /
3.3 V
LVCMOS
12 mA 12 mA High
5
鈥�
1.55 2.67 0.26 0.98 1.10 2.71 2.18 3.25 3.93 8.50 7.97 ns
3.3 V
LVCMOS
Wide
Range2
100 A 12 mA High
5
鈥�
1.55 3.73 0.26 1.32 1.10 3.73 2.91 4.51 5.43 9.52 8.69 ns
2.5 V
LVCMOS
12 mA 12 mA High
5
鈥�
1.55 2.64 0.26 1.20 1.10 2.67 2.29 3.30 3.79 8.46 8.08 ns
1.8 V
LVCMOS
12 mA 12 mA High
5
鈥�
1.55 2.72 0.26 1.11 1.10 2.76 2.43 3.58 4.19 8.55 8.22 ns
1.5 V
LVCMOS
12 mA 12 mA High
5
鈥�
1.55 2.96 0.26 1.27 1.10 3.00 2.70 3.75 4.23 8.78 8.48 ns
1.2 V
LVCMOS
2 mA
High
5
鈥�
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns
1.2 V
LVCMOS
Wide
Range3
100 A
2 mA
High
5
鈥�
1.55 3.60 0.26 1.60 1.10 3.47 3.36 3.93 3.65 9.26 9.14 ns
3.3 V PCI Per PCI
spec
鈥�
High
10 252 1.55 2.91 0.26 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns
3.3 V
PCI-X
Per
PCI-X
spec
鈥�
High
10 252 1.55 2.91 0.25 0.86 1.10 2.95 2.29 3.25 3.93 8.74 8.08 ns
LVDS
24 mA
鈥�
High
鈥�
1.55 2.27 0.25 1.57
鈥�
ns
LVPECL
24 mA
鈥�
High
鈥�
1.55 2.24 0.25 1.38
鈥�
ns
Notes:
1. The minimum drive strength for any LVCMOS 1.2 V or LVCMOS 3.3 V software configuration when run in wide range is
卤100 A. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the
IBIS models.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD-8B specification.
3. All LVCMOS 1.2 V software macros support LVCMOS 1.2 V wide range as specified in the JESD8-12 specification
4. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-12 on page 2-78 for connectivity. This resistor is not required during normal operation.
5. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.