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參數(shù)資料
| 型號： | AGL125-VQ100I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 125000 GATES, PQFP100 |
| 封裝： | 14 X 14MM, 0.50 MM PITCH, GREEN, VQFP-100 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大小： | 234K |
| 代理商： | AGL125-VQ100I |
IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
8
Pr od uct Br ief
Flash*Freeze Technology
The IGLOO device has an ultra-low power static mode
that retains all SRAM and register information and can
still quickly return to normal operation. Flash*Freeze
technology allows the user to quickly enter and exit
Flash*Freeze
mode
within
1 s
by
activating
the
Flash*Freeze pin while all power supplies are kept at
their original values. In addition, I/Os and clocks can still
be driven or can be toggling without impact on power
consumption, and the device retains all core registers,
SRAM information, and states. No power is consumed by
the I/Os, clocks, JTAG pins, or PLL, and the device
consumes as little as 5 W in this mode.
Flash*Freeze technology allows the user to switch to
active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active high) can be routed
internally to the core to allow the user's logic to decide if
it is safe to transition to this mode. It is also possible to
use the Flash*Freeze pin as a regular I/O if the
Flash*Freeze mode usage is not planned, which is
advantageous because of the inherent low power static
(as low as 25 W) and dynamic capabilities of the IGLOO
device. Refer to Figure 3 for an illustration of entering/
exiting Flash*Freeze mode. For more information on
how to use the Flash*Freeze mode, refer to the Low
Figure 2 Device Architecture Overview with Four I/O Banks (AGL250, AGL600, and AGL1000)
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
(AGL600 and AGL1000)
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
VersaTile
CCC
I/Os
ISP AES
Decryption
User Nonvolatile
FlashROM
Charge Pumps
Bank 0
Bank
3
Bank
3
Bank
1
Bank
1
Bank 2
Figure 3 IGLOO Flash*Freeze Mode
Actel IGLOO
FPGA
Flash*Freeze
Mode Control
Flash*Freeze Pin
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL125-VQ100 | FPGA, 125000 GATES, PQFP100 |
| AGL125-VQG100I | FPGA, 125000 GATES, PQFP100 |
| AGL125-VQG100 | FPGA, 125000 GATES, PQFP100 |
| AGLE3000V2-FFG484C | FPGA, 75264 CLBS, 3000000 GATES, PBGA484 |
| AGOF5S3P-20.00MHZ | OCXO, CLOCK, 20 MHz, HCMOS OUTPUT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL250 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:IGLOO Low Power Flash FPGAs with Flash*Freeze Technology |
| AGL250V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL250V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL250V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL250V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
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