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參數(shù)資料
| 型號(hào)： | AGL125-VQ100 |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 125000 GATES, PQFP100 |
| 封裝： | 14 X 14MM, 0.50 MM PITCH, GREEN, VQFP-100 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 234K |
| 代理商： | AGL125-VQ100 |
IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
Pr od uct Br ief
7
Advanced Architecture
The proprietary IGLOO architecture provides granularity
comparable to standard-cell ASICs. The IGLOO device
consists of five distinct and programmable architectural
features (Figure 1 and Figure 2 on page 8):
Flash*Freeze technology
FPGA VersaTiles
Dedicated FlashROM memory
Dedicated SRAM/FIFO memory1
Extensive clock conditioning circuitry (CCC) and
PLLs1
Advanced I/O structure
The FPGA core consists of a sea of VersaTiles. Each
VersaTile can be configured as a three-input logic
function or as a D-flip-flop (with or without enable), or
as a latch, by programming the appropriate Flash switch
interconnections. The versatility of the IGLOO core tile as
either a three-input lookup table (LUT) equivalent or as a
D-flip-flop/latch with enable allows for efficient use of
the FPGA fabric. The VersaTile capability is unique to the
Actel ProASIC families of third generation architecture
Flash FPGAs. VersaTiles are connected with any of the
four levels of routing hierarchy. Flash switches are
distributed
throughout
the
device
to
provide
nonvolatile, reconfigurable interconnect programming.
Maximum core utilization is possible for virtually any
design.
In addition, extensive on-chip programming circuitry
allows for rapid, single-voltage (3.3 V) programming of
the IGLOO devices via an IEEE 1532 JTAG interface.
1. The AGL030 does not support PLL and SRAM.
Note: *Not supported by AGL030
Figure 1 Device Architecture Overview with Two I/O Banks (AGL030, AGL060, and AGL125)
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
VersaTile
CCC
I/Os
ISP AES
Decryption*
User Nonvolatile
FlashROM
Charge Pumps
Bank 0
Bank
1
Bank
1
Bank
0
Bank
0
Bank 1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AGL125-VQG100I | FPGA, 125000 GATES, PQFP100 |
| AGL125-VQG100 | FPGA, 125000 GATES, PQFP100 |
| AGLE3000V2-FFG484C | FPGA, 75264 CLBS, 3000000 GATES, PBGA484 |
| AGOF5S3P-20.00MHZ | OCXO, CLOCK, 20 MHz, HCMOS OUTPUT |
| AH110-89G | 50 MHz - 2000 MHz RF/MICROWAVE WIDE BAND MEDIUM POWER AMPLIFIER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AGL250 | 制造商:MICROSEMI 制造商全稱:Microsemi Corporation 功能描述:IGLOO Low Power Flash FPGAs with Flash*Freeze Technology |
| AGL250V2-CS144 | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL250V2-CS144ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL250V2-CS144I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
| AGL250V2-CS144PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:IGLOO Low-Power Flash FPGAs with Flash Freeze Technology |
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