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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL1000V5-FG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 113/250闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 1M 484FBGA
妯欐簴鍖呰锛� 60
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 24576
RAM 浣嶇附瑷堬細 147456
杓稿叆/杓稿嚭鏁�(sh霉)锛� 300
闁€鏁�(sh霉)锛� 1000000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 484-BGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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IGLOO DC and Switching Characteristics
2-4
Revision 23
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLX exceed brownout
activation levels (see Figure 2-1 and Figure 2-2 on page 2-5 for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V 卤 0.25
V for V5 devices, and 0.75 V 卤 0.2 V for V2 devices), the PLL output lock signal goes low and/or the
output clock is lost. Refer to the Brownout Voltage section in the "Power-Up/-Down Behavior of Low
Power Flash Devices" chapter of the ProASIC3 and ProASIC3E FPGA fabric user鈥檚 guides for
information on clock and lock recovery.
Internal Power-Up Activation Sequence
1. Core
2. Input buffers
3. Output buffers, after 200 ns delay from input buffer activation
To make sure the transition from input buffers to output buffers is clean, ensure that there is no path
longer than 100 ns from input buffer to output buffer in your design.
Figure 2-1 V5 Devices 鈥� I/O State as a Function of VCCI and VCC Voltage Levels
Region 1: I/O buffers are OFF
Region 2: I/O buffers are ON.
I/Os are functional (except differential inputs)
but slower because VCCI / VCC are below
specification. For the same reason, input
buffers do not meet VIH / VIL levels, and
output buffers do not meet VOH / VOL levels.
Min VCCI datasheet specification
voltage at a selected I/O
standard; i.e., 1.425 V or 1.7 V
or 2.3 V or 3.0 V
VCC
VCC = 1.425 V
Region 1: I/O Buffers are OFF
Activation trip point:
V
a = 0.85 V 卤 0.25 V
Deactivation trip point:
V
d = 0.75 V 卤 0.25 V
Activation trip point:
V
a = 0.9 V 卤 0.3 V
Deactivation trip point:
V
d = 0.8 V 卤 0.3 V
VCC = 1.575 V
Region 5: I/O buffers are ON
and power supplies are within
specification.
I/Os meet the entire datasheet
and timer specifications for
speed, VIH / VIL, VOH / VOL,
etc.
Region 4: I/O
buffers are ON.
I/Os are functional
(except differential inputs)
but slower because VCCI
is below specification. For the
same reason, input buffers do not
meet VIH / VIL levels, and output
buffers do not meet VOH / VOL levels.
where VT can be from 0.58 V to 0.9 V (typically 0.75 V)
VCCI
Region 3: I/O buffers are ON.
I/Os are functional; I/O DC
specifications are met,
but I/Os are slower because
the VCC is below specification.
VCC = VCCI + VT
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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