- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗4449 > AGL1000V2-FG484 (Microsemi SoC)IC FPGA 1KB FLASH 1M 484FBGA PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AGL1000V2-FG484 |
| 寤犲晢锛� | Microsemi SoC |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 215/250闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 1KB FLASH 1M 484FBGA |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 绯诲垪锛� | IGLOO |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 24576 |
| RAM 浣嶇附瑷�(j矛)锛� | 147456 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 300 |
| 闁€鏁�(sh霉)锛� | 1000000 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.575 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | 0°C ~ 70°C |
| 灏佽/澶栨锛� | 484-BGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 484-FPBGA锛�23x23锛� |
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IGLOO Low Power Flash FPGAs
Revision 23
2-51
Table 2-69
3.3 V LVCMOS Wide Range Low Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Plus Banks
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1
Speed
Grade tDOUT tDP
tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
100 A
4 mA
Std.
0.97
5.84 0.18 1.20
0.66
5.86 5.04 2.74 2.71 9.46 8.64
ns
100 A
6 mA
Std.
0.97
4.76 0.18 1.20
0.66
4.78 4.33 3.09 3.33 8.37 7.93
ns
100 A
8 mA
Std.
0.97
4.76 0.18 1.20
0.66
4.78 4.33 3.09 3.33 8.37 7.93
ns
100 A
12 mA
Std.
0.97
4.02 0.18 1.20
0.66
4.04 3.78 3.33 3.73 7.64 7.37
ns
100 A
16 mA
Std.
0.97
4.02 0.18 1.20
0.66
4.04 3.78 3.33 3.73 7.64 7.37
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤 100 A. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-70
3.3 V LVCMOS Wide Range High Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Standard Plus Banks
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1
Speed
Grade tDOUT tDP
tDIN tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
100 A
4 mA
Std.
0.97
3.33 0.18 1.20 0.66
3.35 2.68 2.73 2.88 6.94 6.27
ns
100 A
6 mA
Std.
0.97
2.75 0.18 1.20 0.66
2.77 2.17 3.08 3.50 6.36 5.77
ns
100 A
8 mA
Std.
0.97
2.75 0.18 1.20 0.66
2.77 2.17 3.08 3.50 6.36 5.77
ns
100 A
12 mA
Std.
0.97
2.45 0.18 1.20 0.66
2.47 1.92 3.33 3.90 6.06 5.51
ns
100 A
16 mA
Std.
0.97
2.45 0.18 1.20 0.66
2.47 1.92 3.33 3.90 6.06 5.51
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤 100 A. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
3. Software default selection highlighted in gray.
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| CAT25010VI-GT3 | IC EEPROM 1KBIT 10MHZ 8SOIC |
| AMM22DTBH | CONN EDGECARD 44POS R/A .156 SLD |
| M1AGL1000V2-FGG484 | IC FPGA 1KB FLASH 1M 484-FBGA |
| M1AGL1000V2-FG484 | IC FPGA 1KB FLASH 1M 484-FBGA |
| AMM22DTBD | CONN EDGECARD 44POS R/A .156 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AGL1000V2-FG484I | 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 1M 484FBGA RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:IGLOO 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛� |
| AGL1000V2-FGG144 | 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.2-1.5V 144FPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�(j矛):221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241 |
| AGL1000V2-FGG144I | 鍔熻兘鎻忚堪:IC FPGA 1KB FLASH 1M 144FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:IGLOO 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�(j矛):6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FBGA锛�23x23锛� |
| AGL1000V2-FGG144T | 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:AGL1000V2-FGG144T - Trays 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 1M GATES 144FBGA 鍒堕€犲晢:Microsemi Corporation 鍔熻兘鎻忚堪:IC FPGA 97 I/O 144FBGA |
| AGL1000V2-FGG256 | 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.2-1.5V 256FPBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪锛� 绯诲垪:IGLOO 妯�(bi膩o)婧�(zh菙n)鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�(j矛):221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241 |
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