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IGLOO DC and Switching Characteristics
2-114
Revision 23
Table 2-190 IGLOO CCC/PLL Specification
For IGLOO V2 Devices, 1.2 V DC Core Supply Voltage
Parameter
Min.
Typ.
Max.
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
160
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
160
MHz
Delay Increments in Programmable Delay Blocks 1, 2
5803
ps
Number of Programmable Values in Each Programmable Delay Block
32
Serial Clock (SCLK) for Dynamic PLL4,5
60
ns
Input Cycle-to-Cycle Jitter (peak magnitude)
0.25
ns
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter6
LockControl = 0
4
ns
LockControl = 1
3
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 11,2
2.3
20.86
ns
Delay Range in Block: Programmable Delay 21,2
0.863
20.86
ns
Delay Range in Block: Fixed Delay 1, 2, 5
5.7
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Maximum Peak-to-Peak Jitter Data7,8
SSO
49 SSO 89 SSO 169
0.75 MHz to 50 MHz
1.20%
2.00%
3.00%
50 MHz to 160 MHz
5.00%
7.00%
15.00%
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-7 and Table 2-7 on page 2-7 for deratings.
2. TJ = 25掳C, VCC = 1.2 V
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. Maximum value obtained for a Std. speed grade device in Worst-Case Commercial Conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
5. The AGL030 device does not support a PLL.
6. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock edge.
Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter parameter.
7. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying the VCO
period by the per cent jitter. The VCO jitter (in ps) applies to CCC_OUT regardless of the output divider settings. For example, if
the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, regardless of the output divider settings.
8. Measurements done with LVTTL 3.3 V, 8 mA I/O drive strength, and high slew Rate. VCC/VCCPLL = 1.14 V, VQ/PQ/TQ type of
packages, 20 pF load.
9. SSO are outputs that are synchronous to a single clock domain and have clock-to-out times that are within 卤200 ps of each
other. Switching I/Os are placed outside of the PLL bank. Refer to the "Simultaneously Switching Outputs (SSOs) and Printed
Circuit Board Layout" section in the IGLOO FPGA Fabric User鈥檚 Guide.
10.
For definitions of Type 1 and Type 2, refer to the PLL Block Diagram in the "Clock Conditioning Circuits in IGLOO and
ProASIC3 Devices" chapter of the IGLOO FPGA Fabric User鈥檚 Guide.
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