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鍨嬭櫉锛� AGL060V5-CS121I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 214/250闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 1KB FLASH 60K 121-CSP
妯欐簴鍖呰锛� 490
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 1536
RAM 浣嶇附瑷堬細 18432
杓稿叆/杓稿嚭鏁�(sh霉)锛� 96
闁€鏁�(sh霉)锛� 60000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 121-VFBGA锛孋SBGA
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IGLOO DC and Switching Characteristics
2-50
Revision 23
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-67
3.3 V LVCMOS Wide Range Low Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1
Speed
Grade tDOUT tDP tDIN tPY tEOUT tZL
tZH
tLZ
tHZ
tZLS tZHS Units
100 A
4 mA
Std.
0.97
6.61 0.18 1.19 0.66 6.63 5.63 3.15 2.98 10.22 9.23
ns
100 A
6 mA
Std.
0.97
5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66
9.10
8.44
ns
100 A
8 mA
Std.
0.97
5.49 0.18 1.19 0.66 5.51 4.84 3.54 3.66
9.10
8.44
ns
100 A
12 mA
Std.
0.97
4.69 0.18 1.19 0.66 4.71 4.25 3.80 4.10
8.31
7.85
ns
100 A
16 mA
Std.
0.97
4.46 0.18 1.19 0.66 4.48 4.11 3.86 4.21
8.07
7.71
ns
100 A
24 mA
Std.
0.97
4.34 0.18 1.19 0.66 4.36 4.14 3.93 4.64
7.95
7.74
ns
Notes:
1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤 100 A. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-68
3.3 V LVCMOS Wide Range High Slew 鈥� Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V
Applicable to Advanced Banks
Drive
Strength
Equivalent
Software
Default
Drive
Strength
Option1
Speed
Grade tDOUT tDP tDIN
tPY tEOUT tZL
tZH
tLZ
tHZ tZLS tZHS Units
100 A
4 mA
Std.
0.97
3.92 0.18 1.19 0.66
3.94 3.10 3.16 3.17 7.54 6.70
ns
100 A
6 mA
Std.
0.97
3.28 0.18 1.19 0.66
3.30 2.54 3.54 3.86 6.90 6.14
ns
100 A
8 mA
Std.
0.97
3.28 0.18 1.19 0.66
3.30 2.54 3.54 3.86 6.90 6.14
ns
100 A
12 mA
Std.
0.97
2.93 0.18 1.19 0.66
2.95 2.27 3.81 4.30 6.54 5.87
ns
100 A
16 mA
Std.
0.97
2.87 0.18 1.19 0.66
2.89 2.22 3.86 4.41 6.49 5.82
ns
100 A
24 mA
Std.
0.97
2.90 0.18 1.19 0.66
2.92 2.16 3.94 4.86 6.51 5.75
ns
Notes:
1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
2. Software default selection highlighted in gray.
3. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is 卤 100 A. Drive
strengths displayed in software are supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
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AGL060V5-CSG121 鍔熻兘鎻忚堪:IC FPGA IGLOO 1.5V CSG121 RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:IGLOO 妯欐簴鍖呰:60 绯诲垪:XP LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):10000 RAM 浣嶇附瑷�:221184 杓稿叆/杓稿嚭鏁�(sh霉):244 闁€鏁�(sh霉):- 闆绘簮闆诲:1.71 V ~ 3.465 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:388-BBGA 渚涙噳鍟嗚ō鍌欏皝瑁�:388-FPBGA锛�23x23锛� 鍏跺畠鍚嶇ū:220-1241