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鍙冩暩(sh霉)璩囨枡
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寤犲晢锛� Microsemi SoC
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 23/250闋�(y猫)
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IGLOO Low Power Flash FPGAs
Revision 23
2-103
1.2 V DC Core Voltage
Table 2-172 Register Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tCLKQ
Clock-to-Q of the Core Register
1.61
ns
tSUD
Data Setup Time for the Core Register
1.17
ns
tHD
Data Hold Time for the Core Register
0.00
ns
tSUE
Enable Setup Time for the Core Register
1.29
ns
tHE
Enable Hold Time for the Core Register
0.00
ns
tCLR2Q
Asynchronous Clear-to-Q of the Core Register
0.87
ns
tPRE2Q
Asynchronous Preset-to-Q of the Core Register
0.89
ns
tREMCLR
Asynchronous Clear Removal Time for the Core Register
0.00
ns
tRECCLR
Asynchronous Clear Recovery Time for the Core Register
0.24
ns
tREMPRE
Asynchronous Preset Removal Time for the Core Register
0.00
ns
tRECPRE
Asynchronous Preset Recovery Time for the Core Register
0.24
ns
tWCLR
Asynchronous Clear Minimum Pulse Width for the Core Register
0.46
ns
tWPRE
Asynchronous Preset Minimum Pulse Width for the Core Register
0.46
ns
tCKMPWH
Clock Minimum Pulse Width High for the Core Register
0.95
ns
tCKMPWL
Clock Minimum Pulse Width Low for the Core Register
0.95
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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