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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL030V2-VQ100
寤犲晢锛� Microsemi SoC
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鏂囦欢澶у皬锛� 0K
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绯诲垪锛� IGLOO
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闁€鏁�(sh霉)锛� 30000
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 100-TQFP
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IGLOO Low Power Flash FPGAs
Revision 23
2-89
Timing Characteristics
1.5 V DC Core Voltage
1.2 V DC Core Voltage
Table 2-159 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
1.00
ns
tOSUD
Data Setup Time for the Output Data Register
0.51
ns
tOHD
Data Hold Time for the Output Data Register
0.00
ns
tOSUE
Enable Setup Time for the Output Data Register
0.70
ns
tOHE
Enable Hold Time for the Output Data Register
0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.34
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.34
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.24
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.24
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.31
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.
Table 2-160 Output Data Register Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std. Units
tOCLKQ
Clock-to-Q of the Output Data Register
1.52
ns
tOSUD
Data Setup Time for the Output Data Register
1.15
ns
tOHD
Data Hold Time for the Output Data Register
0.00
ns
tOSUE
Enable Setup Time for the Output Data Register
1.11
ns
tOHE
Enable Hold Time for the Output Data Register
0.00
ns
tOCLR2Q
Asynchronous Clear-to-Q of the Output Data Register
1.96
ns
tOPRE2Q
Asynchronous Preset-to-Q of the Output Data Register
1.96
ns
tOREMCLR
Asynchronous Clear Removal Time for the Output Data Register
0.00
ns
tORECCLR
Asynchronous Clear Recovery Time for the Output Data Register
0.24
ns
tOREMPRE
Asynchronous Preset Removal Time for the Output Data Register
0.00
ns
tORECPRE
Asynchronous Preset Recovery Time for the Output Data Register
0.24
ns
tOWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register
0.19
ns
tOWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register
0.19
ns
tOCKMPWH
Clock Minimum Pulse Width High for the Output Data Register
0.31
ns
tOCKMPWL
Clock Minimum Pulse Width Low for the Output Data Register
0.28
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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