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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AGL030V2-QNG132I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 17/250闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1KB FLASH 30K 132-QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 348
绯诲垪锛� IGLOO
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 768
杓稿叆/杓稿嚭鏁�(sh霉)锛� 81
闁€鏁�(sh霉)锛� 30000
闆绘簮闆诲锛� 1.14 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 132-WFQFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 132-QFN锛�8x8锛�
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IGLOO Low Power Flash FPGAs
Revision 23
2-97
1.2 V DC Core Voltage
Table 2-168 Output DDR Propagation Delays
Commercial-Case Conditions: TJ = 70掳C, Worst-Case VCC = 1.14 V
Parameter
Description
Std.
Units
tDDROCLKQ
Clock-to-Out of DDR for Output DDR
1.60
ns
tDDROSUD1
Data_F Data Setup for Output DDR
1.09
ns
tDDROSUD2
Data_R Data Setup for Output DDR
1.16
ns
tDDROHD1
Data_F Data Hold for Output DDR
0.00
ns
tDDROHD2
Data_R Data Hold for Output DDR
0.00
ns
tDDROCLR2Q
Asynchronous Clear-to-Out for Output DDR
1.99
ns
tDDROREMCLR
Asynchronous Clear Removal Time for Output DDR
0.00
ns
tDDRORECCLR
Asynchronous Clear Recovery Time for Output DDR
0.24
ns
tDDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR
0.19
ns
tDDROCKMPWH
Clock Minimum Pulse Width High for the Output DDR
0.31
ns
tDDROCKMPWL
Clock Minimum Pulse Width Low for the Output DDR
0.28
ns
FDDOMAX
Maximum Frequency for the Output DDR
160.00
MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.
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