Revision 4 2-221 Output Enable Register Timing Characteristics Figure 2-141 Output Enabl" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AFS600-FGG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 154/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 4MB FLASH 600K 484FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� Fusion®
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 172
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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Fusion Family of Mixed Signal FPGAs
Revision 4
2-221
Output Enable Register
Timing Characteristics
Figure 2-141 Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
tOESUE
50%
tOESUD tOEHD
50%
tOECLKQ
1
0
tOEHE
tOERECPRE
tOEREMPRE
tOERECCLR
tOEREMCLR
tOEWCLR
tOEWPRE
tOEPRE2Q
tOECLR2Q
tOECKMPWH tOECKMPWL
50%
Table 2-178 Output Enable Register Propagation Delays
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.44 0.51
0.59
ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36
0.42
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00
0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
0.44 0.50
0.58
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00 0.00
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76
0.89
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76
0.89
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25
0.30
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25
0.30
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable
Register
0.22 0.25
0.30
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable
Register
0.22 0.25
0.30
ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
0.36 0.41
0.48
ns
tOECKMPWL
Clock Minimum Pulse Width Low for the Output Enable Register
0.32 0.37
0.43
ns
Note: For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
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