2-120 Revision 4 Analog System Characteristics Table 2-49 Analog Channel Specifications Commercial Te" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AFS600-FG484
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 42/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 4MB FLASH 600K 484FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 60
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 172
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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Device Architecture
2-120
Revision 4
Analog System Characteristics
Table 2-49 Analog Channel Specifications
Commercial Temperature Range Conditions, TJ = 85掳C (unless noted otherwise),
Typical: VCC33A = 3.3 V, VCC = 1.5 V
Parameter
Description
Condition
Min.
Typ.
Max.
Units
Voltage Monitor Using Analog Pads AV, AC and AT (using prescaler)
Input Voltage
(Prescaler)
VINAP
Uncalibrated Gain and
Offset Errors
Refer to Table 2-51 on
Calibrated Gain and
Offset Errors
Refer to Table 2-52 on
Bandwidth1
100
KHz
Input Resistance
Scaling Factor
Prescaler modes (Table 2-57 on
Sample Time
10
s
Current Monitor Using Analog Pads AV and AC
VRSM1
Maximum Differential
Input Voltage
VAREF / 10
mV
Resolution
Common Mode Range
鈥� 10.5 to +12
V
CMRR
Common Mode
Rejection Ratio
DC 鈥� 1 KHz
60
dB
1 KHz - 10 KHz
50
dB
> 10 KHz
30
dB
tCMSHI
Strobe High time
ADC
conv.
time
200
s
tCMSHI
Strobe Low time
5
s
tCMSHI
Settling time
0.02
s
Accuracy
Input differential voltage > 50 mV
鈥�2 鈥�(0.05 x
VRSM) to +2 +
(0.05 x VRSM)
mV
Notes:
1. VRSM is the maximum voltage drop across the current sense resistor.
2. Analog inputs used as digital inputs can tolerate the same voltage limits as the corresponding analog pad. There is no
reliability concern on digital inputs as long as VIND does not exceed these limits.
3. VIND is limited to VCC33A + 0.2 to allow reaching 10 MHz input frequency.
4. An averaging of 1,024 samples (LPF setting in Analog System Builder) is required and the maximum capacitance
allowed across the AT pins is 500 pF.
5. The temperature offset is a fixed positive value.
6. The high current mode has a maximum power limit of 20 mW. Appropriate current limit resistors must be used, based on
voltage on the pad.
7. When using SmartGen Analog System Builder, CalibIP is required to obtain 0 offset. For further details on CalibIP, refer
to the "Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the Fusion FPGA Fabric User鈥檚
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