3-18 Revision 4 Power per I/O Pin Table 3-12 Summary of I/O Input Buffer Power (per pin)鈥擠efault I/O Software" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AFS600-2PQG208I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 188/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 4MB FLASH 600K 208PQFP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 24
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 95
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 208-BFQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 208-PQFP锛�28x28锛�
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DC and Power Characteristics
3-18
Revision 4
Power per I/O Pin
Table 3-12 Summary of I/O Input Buffer Power (per pin)鈥擠efault I/O Software Settings
VCCI (V)
Static Power
PDC7 (mW)1
Dynamic Power
PAC9 (W/MHz)2
Applicable to Pro I/O Banks
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
鈥�
17.39
3.3 V LVTTL/LVCMOS 鈥� Schmitt trigger
3.3
鈥�
25.51
2.5 V LVCMOS
2.5
鈥�
5.76
2.5 V LVCMOS 鈥� Schmitt trigger
2.5
鈥�
7.16
1.8 V LVCMOS
1.8
鈥�
2.72
1.8 V LVCMOS 鈥� Schmitt trigger
1.8
鈥�
2.80
1.5 V LVCMOS (JESD8-11)
1.5
鈥�
2.08
1.5 V LVCMOS (JESD8-11) 鈥� Schmitt trigger
1.5
鈥�
2.00
3.3 V PCI
3.3
鈥�
18.82
3.3 V PCI 鈥� Schmitt trigger
3.3
鈥�
20.12
3.3 V PCI-X
3.3
鈥�
18.82
3.3 V PCI-X 鈥� Schmitt trigger
3.3
鈥�
20.12
Voltage-Referenced
3.3 V GTL
3.3
2.90
8.23
2.5 V GTL
2.5
2.13
4.78
3.3 V GTL+
3.3
2.81
4.14
2.5 V GTL+
2.5
2.57
3.71
HSTL (I)
1.5
0.17
2.03
HSTL (II)
1.5
0.17
2.03
SSTL2 (I)
2.5
1.38
4.48
SSTL2 (II)
2.5
1.38
4.48
SSTL3 (I)
3.3
3.21
9.26
SSTL3 (II)
3.3
3.21
9.26
Differential
LVDS
2.5
2.26
1.50
LVPECL
3.3
5.71
2.17
Notes:
1. PDC7 is the static power (where applicable) measured on VCCI.
2. PAC9 is the total dynamic power measured on VCC and VCCI.
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