2-24 Revision 4 Notes: 1. Visit the Microsemi SoC Products Group website for application notes concerning dynamic PL" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AFS600-1FG256
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 270/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 4MB FLASH 600K 256FBGA
妯欐簴鍖呰锛� 90
绯诲垪锛� Fusion®
RAM 浣嶇附瑷堬細 110592
杓稿叆/杓稿嚭鏁�(sh霉)锛� 119
闁€鏁�(sh霉)锛� 600000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 256-LBGA
渚涙噳鍟嗚ō鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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Device Architecture
2-24
Revision 4
Notes:
1. Visit the Microsemi SoC Products Group website for application notes concerning dynamic PLL reconfiguration. Refer to
the "PLL Macro" section on page 2-29 for signal descriptions.
2. Many specific INBUF macros support the wide variety of single-ended and differential I/O standards for the Fusion family.
Figure 2-19 Fusion CCC Options: Global Buffers with the PLL Macro
Table 2-11 Available Selections of I/O Standards within CLKBUF and CLKBUF_LVDS/LVPECL Macros
CLKBUF Macros
CLKBUF_LVCMOS5
CLKBUF_LVCMOS331
CLKBUF_LVCMOS18
CLKBUF_LVCMOS15
CLKBUF_PCI
CLKBUF_LVDS2
CLKBUF_LVPECL
Notes:
1. This is the default macro. For more details, refer to the IGLOO, ProASIC3, SmartFusion and Fusion Macro Library
Guide.
2. The B-LVDS and M-LVDS standards are supported with CLKBUF_LVDS.
PADN
PADP
Y
PAD
Y
Input LVDS/LVPECL Macro
INBUF2 Macro
GLA
or
GLA and (GLB or YB)
or
GLA and (GLC or YC)
or
GLA and (GLB or YB) and
(GLC or YC)
Clock Source
Clock Conditioning
Output
OADIVHALF
OADIV[4:0]
OAMUX[2:0]
DLYGLA[4:0]
OBDIV[4:0]
OBMUX[2:0]
DLYYB[4:0]
DLYGLB[4:0]
OCDIV[4:0]
OCMUX[2:0]
DLYYC[4:0]
DLYGLC[4:0]
FINDIV[6:0]
FBDIV[6:0]
FBDLY[4:0]
FBSEL[1:0]
XDLYSEL
VCOSEL[2:0]
CLKA
EXTFB
POWERDOWN
OADIVRST
GLA
LOCK
GLB
YB
GLC
YC
鐩搁棞PDF璩囨枡
PDF鎻忚堪
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