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參數(shù)資料
| 型號(hào)： | AFS250-2QNG180I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 21/334頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 2MB FLASH 250K 180-QFN |
| 標(biāo)準(zhǔn)包裝： | 184 |
| 系列： | Fusion® |
| RAM 位總計(jì)： | 36864 |
| 輸入/輸出數(shù)： | 65 |
| 門數(shù)： | 250000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 180-WFQFN |
| 供應(yīng)商設(shè)備封裝： | 180-QFN（10x10） |
Fusion Family of Mixed Signal FPGAs
Revision 4
2-101
There are several popular ADC architectures, each with advantages and limitations. The analog-to-digital
converter in Fusion devices is a switched-capacitor Successive Approximation Register (SAR) ADC. It
supports 8-, 10-, and 12-bit modes of operation with a cumulative sample rate up to 600 k samples per
second (ksps). Built-in bandgap circuitry offers 1% internal voltage reference accuracy or an external
reference voltage can be used.
As shown in Figure 2-81, a SAR ADC contains N capacitors with binary-weighted values.
To begin a conversion, all of the capacitors are quickly discharged. Then VIN is applied to all the
capacitors for a period of time (acquisition time) during which the capacitors are charged to a value very
close to VIN. Then all of the capacitors are switched to ground, and thus –VIN is applied across the
comparator. Now the conversion process begins. First, C is switched to VREF. Because of the binary
weighting of the capacitors, the voltage at the input of the comparator is then shown by EQ 11.
Voltage at input of comparator = –VIN + VREF / 2
EQ 11
If VIN is greater than VREF / 2, the output of the comparator is 1; otherwise, the comparator output is 0.
A register is clocked to retain this value as the MSB of the result. Next, if the MSB is 0, C is switched
back to ground; otherwise, it remains connected to VREF, and C / 2 is connected to VREF. The result at
the comparator input is now either –VIN + VREF / 4 or –VIN + 3 VREF / 4 (depending on the state of the
MSB), and the comparator output now indicates the value of the next most significant bit. This bit is
likewise registered, and the process continues for each subsequent bit until a conversion is completed.
The conversion process requires some acquisition time plus N + 1 ADC clock cycles to complete.
Figure 2-81 Example SAR ADC Architecture
Comparator
C
C / 2
C / 4
C / 2N–2
C / 2N–1
VREF
VIN
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AFS250-2QNG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2QNG256I | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-2QNG256PP | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| AFS250-FFG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 250K GATES 130NM 1.5V 256FBGA - Trays |
| AFS250-FFG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
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