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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AFS250-1QNG180I
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 304/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 2MB FLASH 250K 180-QFN
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 184
绯诲垪锛� Fusion®
RAM 浣嶇附瑷堬細 36864
杓稿叆/杓稿嚭鏁�(sh霉)锛� 65
闁€鏁�(sh霉)锛� 250000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 180-WFQFN
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 180-QFN锛�10x10锛�
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Fusion Family of Mixed Signal FPGAs
Revision 4
2-55
tSUPGLOSSPRO
Page Loss Protect Setup Time for the Control Logic
1.69
1.93
2.27
ns
tHDPGLOSSPRO
Page Loss Protect Hold Time for the Control Logic
0.00
ns
tSUPGSTAT
Page Status Setup Time for the Control Logic
2.49
2.83
3.33
ns
tHDPGSTAT
Page Status Hold Time for the Control Logic
0.00
ns
tSUOVERWRPG
Over Write Page Setup Time for the Control Logic
1.88
2.14
2.52
ns
tHDOVERWRPG
Over Write Page Hold Time for the Control Logic
0.00
ns
tSULOCKREQUEST
Lock Request Setup Time for the Control Logic
0.87
0.99
1.16
ns
tHDLOCKREQUEST
Lock Request Hold Time for the Control Logic
0.00
ns
tRECARNVM
Reset Recovery Time
0.94
1.07
1.25
ns
tREMARNVM
Reset Removal Time
0.00
ns
tMPWARNVM
Asynchronous Reset Minimum Pulse Width for the
Control Logic
10.00
12.50
ns
tMPWCLKNVM
Clock Minimum Pulse Width for the Control Logic
4.00
5.00
ns
tFMAXCLKNVM
Maximum Frequency for Clock for the Control Logic 鈥� for
AFS1500/AFS600
80.00
MHz
Maximum Frequency for Clock for the Control Logic 鈥� for
AFS250/AFS090
100.00
80.00
MHz
Table 2-25 Flash Memory Block Timing (continued)
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
鐩搁棞(gu膩n)PDF璩囨枡
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