2-18 Revision 4 Table 2-7 AFS250 Global Resource Timing Commercial Temperature Range Conditions: T
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AFS1500-FGG256K
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 263/334闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 8MB FLASH 1.5M 256-FBGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� Fusion®
RAM 浣嶇附瑷�(j矛)锛� 276480
杓稿叆/杓稿嚭鏁�(sh霉)锛� 119
闁€鏁�(sh霉)锛� 1500000
闆绘簮闆诲锛� 1.425 V ~ 1.575 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -55°C ~ 100°C
灏佽/澶栨锛� 256-LBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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Device Architecture
2-18
Revision 4
Table 2-7 AFS250 Global Resource Timing
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
Min.1
Max.2 Min.1
Max.2
Min.1
Max.2
tRCKL
Input Low Delay for Global Clock
0.89
1.12
1.02
1.27
1.20
1.50
ns
tRCKH
Input High Delay for Global Clock
0.88
1.14
1.00
1.30
1.17
1.53
ns
tRCKMPWH
Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.26
0.30
0.35
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.
Table 2-8 AFS090 Global Resource Timing
Commercial Temperature Range Conditions: TJ = 70掳C, Worst-Case VCC = 1.425 V
Parameter
Description
鈥�2
鈥�1
Std.
Units
Min.1
Max.2
Min.1 Max.2 Min.1 Max.2
tRCKL
Input Low Delay for Global Clock
0.84
1.07
0.96
1.21
1.13
1.43
ns
tRCKH
Input High Delay for Global Clock
0.83
1.10
0.95
1.25
1.12
1.47
ns
tRCKMPWH Minimum Pulse Width High for Global Clock
ns
tRCKMPWL
Minimum Pulse Width Low for Global Clock
ns
tRCKSW
Maximum Skew for Global Clock
0.27
0.30
0.36
ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on page 3-9.
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