鍨嬭櫉锛� | AFS1500-1FGG256I |
寤犲晢锛� | Microsemi SoC |
鏂囦欢闋佹暩(sh霉)锛� | 11/334闋� |
鏂囦欢澶�?銆�?/td> | 0K |
鎻忚堪锛� | IC FPGA 8MB FLASH 1.5M 256-FBGA |
妯欐簴鍖呰锛� | 90 |
绯诲垪锛� | Fusion® |
RAM 浣嶇附瑷堬細 | 276480 |
杓稿叆/杓稿嚭鏁�(sh霉)锛� | 119 |
闁€鏁�(sh霉)锛� | 1500000 |
闆绘簮闆诲锛� | 1.425 V ~ 1.575 V |
瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
宸ヤ綔婧害锛� | -40°C ~ 100°C |
灏佽/澶栨锛� | 256-LBGA |
渚涙噳鍟嗚ō鍌欏皝瑁濓細 | 256-FPBGA锛�17x17锛� |
鐩搁棞PDF璩囨枡 |
PDF鎻忚堪 |
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A42MX36-BGG272I | IC FPGA MX SGL CHIP 54K 272-PBGA |
A42MX36-BG272I | IC FPGA MX SGL CHIP 54K 272-PBGA |
A42MX36-1PQG240I | IC FPGA MX SGL CHIP 54K 240-PQFP |
A42MX36-1PQ240I | IC FPGA MX SGL CHIP 54K 240-PQFP |
A1240A-TQ176C | IC FPGA 4K GATES 176-TQFP COM |
鐩搁棞浠g悊鍟�/鎶€琛撳弮鏁�(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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AFS1500-1FGG256K | 鍔熻兘鎻忚堪:IC FPGA 8MB FLASH 1.5M 256-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Fusion® 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳鍟嗚ō鍌欏皝瑁�:352-CQFP锛�75x75锛� |
AFS1500-1FGG256PP | 鍒堕€犲晢:ACTEL 鍒堕€犲晢鍏ㄧū:Actel Corporation 鍔熻兘鎻忚堪:Actel Fusion Mixed-Signal FPGAs |
AFS1500-1FGG484 | 鍔熻兘鎻忚堪:IC FPGA 8MB FLASH 1.5M 484-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Fusion® 鐢�(ch菐n)鍝佸煿瑷撴ā濉�:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 鐗硅壊鐢�(ch菐n)鍝�:Cyclone? IV FPGAs 妯欐簴鍖呰:60 绯诲垪:CYCLONE® IV GX LAB/CLB鏁�(sh霉):9360 閭忚集鍏冧欢/鍠厓鏁�(sh霉):149760 RAM 浣嶇附瑷�:6635520 杓稿叆/杓稿嚭鏁�(sh霉):270 闁€鏁�(sh霉):- 闆绘簮闆诲:1.16 V ~ 1.24 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 85°C 灏佽/澶栨:484-BGA 渚涙噳鍟嗚ō鍌欏皝瑁�:484-FBGA锛�23x23锛� |
AFS1500-1FGG484I | 鍔熻兘鎻忚堪:IC FPGA 8MB FLASH 1.5M 484-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Fusion® 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳鍟嗚ō鍌欏皝瑁�:352-CQFP锛�75x75锛� |
AFS1500-1FGG484K | 鍔熻兘鎻忚堪:IC FPGA 8MB FLASH 1.5M 484-FBGA RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪锛� 绯诲垪:Fusion® 妯欐簴鍖呰:1 绯诲垪:ProASICPLUS LAB/CLB鏁�(sh霉):- 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:129024 杓稿叆/杓稿嚭鏁�(sh霉):248 闁€鏁�(sh霉):600000 闆绘簮闆诲:2.3 V ~ 2.7 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:- 灏佽/澶栨:352-BFCQFP锛屽付鎷夋】 渚涙噳鍟嗚ō鍌欏皝瑁�:352-CQFP锛�75x75锛� |