參數(shù)資料
型號： AFE7222IRGCT
廠商： Texas Instruments
文件頁數(shù)： 21/106頁
文件大?。?/td> 0K
描述： IC AFE 12BIT 65/130MSPS 64VQFN
標準包裝： 1
位數(shù)： 12
通道數(shù)： 4
功率（瓦特）： 610mW
電壓 - 電源，模擬： 2.85 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.7 V ~ 1.9 V
封裝/外殼： 64-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 64-VQFN 裸露焊盤（9x9）
包裝： 標準包裝
其它名稱： 296-30113-6
Q
M
C
O
ff
s
e
t
C
o
a
rs
e
M
ix
e
r
(C
M
IX
)
2
x
In
te
rp
o
la
ti
o
n
T
x
F
IR
2
x
In
te
rp
o
la
ti
o
n
T
x
F
IR
1
In
v
e
rs
e
S
IN
C
Q
M
C
G
a
in
/
P
h
a
s
e
F
in
e
M
ix
e
r
8
d
e
p
F
IF
O
NCO
SYNC
TX A input
(I channel)
TX B input
(Q channel)
TX A output
TX B output
DAC_DCLKIN
DAC_CLK
%1,2,4
DAC_CLK
SLOS711B – NOVEMBER 2011 – REVISED MARCH 2012
5
REGISTER DESCRIPTIONS
5.1
TRANSMIT DIGITAL SIGNAL CHAIN REGISTERS
Figure 5-1. Signal Chain
Input data is shifted into the 8-deep FIFO at the rate of DAC_DCLKIN. At its output, the FIFO hands off
the data using a divided version of the DAC_CLK (based on the interpolation factor). The rest of the signal
chain runs off DAC_CLK and its divided derivatives.
Register Name – CONFIG0 – Address 0x103, Default = 0x00
<7>
<6>
<5>
<4>
<3>
<2>
<1>
<0>
Tx_BYP_SRC
TX_BYP
TX_ChB_PDN_SRC
TX_CHB_PDN
TX_CHA_PDN_SRC
TX_CHA_PDN
TX_DIS
TX_DIS – Disables the digital signal chain of both channels in TX . All blocks in digital signal chain are
powered down, and the output is DAC mid-code. Note: the DACs are not powered down in this mode.
TX_CHA_PDN – Powers down digital signal chain of Channel A in Tx . Output of the channel is mid code.
Set TX_CHA_PDN_SRC for this to take effect.
TX_CHA_PDN_SRC – Setting this causes the value programmed into TX_CHA_PDN to take effect.
TX_CHB_PDN – Powers down digital signal chain of Channel B in Tx . Output of the channel is mid code.
Set TX_CHB_PDN_SRC for this to take effect.
TX_CHB_PDN_SRC – Setting this causes the value programmed into TX_CHB_PDN to take effect.
Note that when in default mode of operation (none of the register-selectable digital features enabled), all 4
of above bits (TX_CHA_PDN, TX_CHA_PDN_SRC, TX_CHB_PDN, TX_CHB_PDN_SRC) have to be set
together to '1' for them to take effect. However, if any of the digital features (like interpolation, Fine mixer,
Coarse mixer, or QMC gain/phase or offset) are enabled, then the channel A can be independently
powered down using bits TX_CHA_PDN and TX_CHA_PDN_SRC, and channel B can be independently
powered down using bits TX_CHB_PDN and TX_CHB_PDN_SRC.
TX_BYP – The inputs to both the Tx channels are directly passed to the outputs. FIFO is bypassed. Set
TX_BYP_SRC for this to take effect.
TX_BYP_SRC – Setting this causes the value programmed into TX_BYP to take effect.
Copyright 2011–2012, Texas Instruments Incorporated
REGISTER DESCRIPTIONS
21
Product Folder Link(s): AFE7222 AFE7225
相關(guān)PDF資料
PDF描述
ALD2502PBL IC TIMER CMOS DUAL HS 14PDIP
ALD4501PEL IC TIMER PREC CMOS QUAD 20PDIP
ALD500AUSWCL IC ADC 18BIT DUAL 16WSOIC
ALD500RAU-10SEL IC ADC 18BIT 20SOIC
ALD555PAL IC TIMER PREC CMOS SGL HS 8PDIP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AFE7225 制造商:TI 制造商全稱:Texas Instruments 功能描述:Analog Front End Wideband Mixed-Signal Transceiver
AFE7225EVM 功能描述:射頻開發(fā)工具 AFE7225 Eval Mod RoHS:否 制造商:Taiyo Yuden 產(chǎn)品:Wireless Modules 類型:Wireless Audio 工具用于評估:WYSAAVDX7 頻率: 工作電源電壓:3.4 V to 5.5 V
AFE7225IRGC25 功能描述:射頻前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數(shù)據(jù)速率:54 Mbps 噪聲系數(shù): 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-32
AFE7225IRGCR 功能描述:射頻前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數(shù)據(jù)速率:54 Mbps 噪聲系數(shù): 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-32
AFE7225IRGCT 功能描述:射頻前端 Dual 12B,125MSPS ADC RoHS:否 制造商:Skyworks Solutions, Inc. 類型: 工作頻率:2.4 GHz, 5 GHz 最大數(shù)據(jù)速率:54 Mbps 噪聲系數(shù): 工作電源電壓:3.3 V 電源電流:180 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-32
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*