參數(shù)資料
型號： ADZS-BF537-EZLITE
廠商： Analog Devices Inc
文件頁數(shù)： 17/68頁
文件大?。?/td> 0K
描述： BOARD EVAL ADSP-BF537
產(chǎn)品培訓(xùn)模塊： Interfacing AV Converters to Blackfin Processors
Blackfin® Processor Core Architecture Overview
Blackfin® Device Drivers
Blackfin® Optimizations for Performance and Power Consumption
Blackfin® System Services
Introduction to VisualDSP++® Tools
特色產(chǎn)品： Blackfin? BF50x Series Processors
標(biāo)準(zhǔn)包裝： 1
系列： Blackfin®
類型： DSP
適用于相關(guān)產(chǎn)品： ADSP-BF537
所含物品： 評估板、軟件和說明文檔
配用： ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARD
ADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE
ADZS-USBLAN-EZEXT-ND - BOARD DAUGHTER EXTENDED USB-LAN
ADZS-BFFPGA-EZEXT-ND - BOARD EVAL FPGA BLACKFIN EXTENDR
相關(guān)產(chǎn)品： ADSP-BF537KBCZ-6BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBCZ-5BV-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537KBCZ-6AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5AV-ND - IC DSP CTLR 16BIT 182CSPBGA
ADSP-BF537BBCZ-5B-ND - IC DSP CTLR 16BIT 208CSPBGA
ADSP-BF537BBC-5A-ND - IC DSP CTLR 16BIT 182CSPBGA
Rev. J
|
Page 24 of 68
|
February 2014
Table 10 through Table 12 describe the voltage/frequency
requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537
processor clocks. Take care in selecting MSEL, SSEL, and CSEL
ratios so as not to exceed the maximum core clock and system
clock. Table 13 describes phase-locked loop operating
conditions.
Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades1
Parameter
Internal Regulator Setting
Max
Unit
fCCLK
Core Clock Frequency (VDDINT =1.30 V Minimum)
2
1.30 V
600
MHz
fCCLK
Core Clock Frequency (VDDINT = 1.20 V Minimum)
3
1.25 V
533
MHz
fCCLK
Core Clock Frequency (VDDINT =1.14 V Minimum)
1.20 V
500
MHz
fCCLK
Core Clock Frequency (VDDINT =1.045 V Minimum)
1.10 V
444
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.95 V Minimum)
1.00 V
400
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.85 V Minimum)
0.90 V
333
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.8 V Minimum)
0.85 V
250
MHz
2 Applies to 600 MHz models only. See Ordering Guide on Page 67.
3 Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 67.
Table 11. Core Clock Requirements—400 MHz Speed Grade1
120°C
T
J 105°C
All2 Other TJ
Unit
Parameter
Internal Regulator Setting
Max
fCCLK
Core Clock Frequency (VDDINT =1.14 V Minimum) 1.20 V
400
MHz
fCCLK
Core Clock Frequency (VDDINT =1.045 V Minimum) 1.10 V
333
363
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.95 V Minimum) 1.00 V
295
333
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.85 V Minimum) 0.90 V
280
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.8 V Minimum) 0.85 V
250
MHz
Table 12. Core Clock Requirements—300 MHz Speed Grade1
Parameter
Internal Regulator Setting
Max
Unit
fCCLK
Core Clock Frequency (VDDINT =1.14 V Minimum)
1.20 V
300
MHz
fCCLK
Core Clock Frequency (VDDINT =1.045 V Minimum)
1.10 V
255
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.95 V Minimum)
1.00 V
210
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.85 V Minimum)
0.90 V
180
MHz
fCCLK
Core Clock Frequency (VDDINT = 0.8 V Minimum)
0.85 V
160
MHz
Table 13. Phase-Locked Loop Operating Conditions
Parameter
Min
Max
Unit
fVCO
Voltage Controlled Oscillator (VCO) Frequency
50
Max fCCLK
MHz
Table 14. System Clock Requirements
Parameter
Condition
Max
Unit
fSCLK
1
VDDEXT 3.3 V or 2.5 V, VDDINT 1.14 V
133
2
MHz
fSCLK
VDDEXT 3.3 V or 2.5 V, VDDINT 1.14 V
100
MHz
1 fSCLK must be less than or equal to fCCLK and is subject to additional restrictions for SDRAM interface operation. See Table 27 on Page 34.
2 Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 27 on Page 34.
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參數(shù)描述
ADZS-BF537-STAMP 功能描述:SYSTEM DEV FOR ADSP-BF537 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
ADZS-BF537-STAMP 制造商:Analog Devices 功能描述:Microcontroller Development Tool
ADZS-BF538-EZLITE 制造商:Analog Devices 功能描述:- Bulk
ADZSBF538FEZLITE 制造商:Analog Devices 功能描述:RES Wirewound 6927 75Ohm 1% 3W 20PPM SMD T/R
ADZS-BF538F-EZLITE 功能描述:BOARD EVAL FOR ADSP-BF538 RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 通用嵌入式開發(fā)板和套件（MCU、DSP、FPGA、CPLD等） 系列:Blackfin® 產(chǎn)品培訓(xùn)模塊:Blackfin® Processor Core Architecture Overview Blackfin® Device Drivers Blackfin® Optimizations for Performance and Power Consumption Blackfin® System Services 特色產(chǎn)品:Blackfin? BF50x Series Processors 標(biāo)準(zhǔn)包裝:1 系列:Blackfin® 類型:DSP 適用于相關(guān)產(chǎn)品:ADSP-BF548 所含物品:板，軟件，4x4 鍵盤，光學(xué)撥輪，QVGA 觸摸屏 LCD 和 40G 硬盤 配用:ADZS-BFBLUET-EZEXT-ND - EZ-EXTENDER DAUGHTERBOARDADZS-BFLLCD-EZEXT-ND - BOARD EXT LANDSCAP LCD INTERFACE 相關(guān)產(chǎn)品:ADSP-BF542BBCZ-4A-ND - IC DSP 16BIT 400MHZ 400CSBGAADSP-BF544MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF542KBCZ-6A-ND - IC DSP 16BIT 600MHZ 400CSBGAADSP-BF547MBBCZ-5M-ND - IC DSP 16BIT 533MHZ MDDR 400CBGAADSP-BF548BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF547BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF544BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGAADSP-BF542BBCZ-5A-ND - IC DSP 16BIT 533MHZ 400CSBGA
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