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參數(shù)資料
| 型號(hào)： | ADV7403KSTZ-1402 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer |
| 中文描述： | 12位，綜合，多格式標(biāo)清/高清視頻解碼器和RGB圖形數(shù)字化儀 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 259K |
| 代理商： | ADV7403KSTZ-1402 |
ADV7403
DETAILED DESCRIPTION
ANALOG FRONT END
The ADV7403 analog front end comprises four Noise Shaped
Video, 12-bit ADCs that digitize the analog video signal before
applying it to the SDP or CP (See Table 8 for sampling rates).
The analog front end uses differential channels to each ADC to
ensure high performance in a mixed-signal application.
Rev. SpA | Page 15 of 24
The front end also includes a 12-channel input mux that enables
multiple video signals to be applied to the ADV7403. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping either in the CP or SDP.
Optional antialiasing filters are positioned in front of each
ADC. These filters can be used to band-limit standard
definition video signals, removing spurious, out-of-band noise.
The ADCs are configured to run in 4× oversampling mode
when decoding composite and S-video inputs; 2× oversampling
is performed for component 525i, 625i, 525p, and 625p sources.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
anti-aliasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
The ADV7403 can support simultaneous processing of CVBS
and RGB standard definition signals to enable SCART compat-
ibility and overlay functionality. A combination of CVBS and
RGB inputs can be mixed and output under control of I
2
C
registers and the fast blank pin.
Table 8: Maximum ADC Sampling Rates
Model
ADV7403BSTZ-110
ADV7403KSTZ-140
Maximum ADC Sampling Rate
110 MHz
140MHz
STANDARD DEFINITION PROCESSOR
The SDP section is capable of decoding a large selection of
baseband video signals in composite S-video and YUV
formats. The video standards supported by the SDP include
PAL B/D/I/G/H, PAL60, PAL M, PAL N, NTSC M/J, NTSC
4.43, and SECAM B/D/G/K/L. The ADV7403 can automatically
detect the video standard and process it accordingly.
The SDP has a 5-line super adaptive 2-D comb filter that gives
superior chrominance and luminance separation when decod-
ing a composite video signal. This highly adaptive filter auto-
matically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
The SDP has an IF filter block that compensates for attenuation
in the high frequency luma spectrum due to tuner SAW filter.
The SDP has specific luminance and chrominance parameter
control for brightness, contrast, saturation, and hue.
The ADV7403 implements a patented adaptive-digital-line-
length-tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7403 to track and decode poor quality video sources such as
VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The SDP also contains a chroma transient
improvement (CTI) processor. This processor increases the edge
rate on chroma transitions, resulting in a sharper video image.
The SDP can process a variety of VBI data services, such as
TeleText, closed captioning (CC), wide screen signaling (WSS),
video programming system (VPS), vertical interval time codes
(VITC), copy generation management system (CGMS), Gemstar
1×/2×, and extended data service (XDS). The ADV7403 SDP
section has a Macrovision 7.1 detection circuit that allows it to
detect Types I, II, and III protection levels. The decoder is also
fully robust to all Macrovision signal inputs.
COMPONENT PROCESSOR
The CP section is capable of decoding/digitizing a wide range of
component video formats in any color space. Component video
standards supported by the CP are 525i, 625i, 525p, 625p, 720p,
1080i, 1250i, VGA up to SXGA @ 75 Hz, (ADV7403KSTZ-140
only) and many other standards not listed here.
The CP section of the ADV7403 contains an AGC block.
When no embedded sync is present, the video gain can be set
manually. The AGC section is followed by a digital clamp
circuit that ensures the video signal is clamped to the correct
blanking level. Automatic adjustments within the CP include
gain (contrast) and offset (brightness); manual adjustment
controls are also supported.
A fully programmable any-to-any, 3 × 3 color space conversion
matrix is placed between the analog front end and the CP
section. This enables YPrPb-to-RGB and RGB-to-YCrCb
conversions. Many other standards of color space can be
implemented using the color space converter.
The output section of the CP is highly flexible. It can be config-
ured in single data rate mode (SDR) with one data packet per
clock cycle or in a double data rate (DDR) mode where data is
presented on the rising and falling edges of the clock. In SDR
mode, a 16-/20-bit 4:2:2 or 24-/30-bit 4:4:4 output is possible. In
these modes, HS, VS, and FIELD/DE (where applicable) timing
reference signals are provided. In DDR mode, the ADV7403 can
be configured in an 8-/10-bit 4:2:2 YcrCb or 12-bit 4:4:4 RGB/
YcrCb pixel output interface with corresponding timing signals.
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