參數(shù)資料
型號(hào)： ADV7393BCPZ-REEL
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： COLOR SIGNAL ENCODER, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFSCP-40
文件頁(yè)數(shù)： 16/96頁(yè)
文件大?。?/td> 1209K
代理商： ADV7393BCPZ-REEL
ADV7390/ADV7391/ADV7392/ADV7393
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
Rev. 0 | Page 16 of 96
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
V
DD_IO
P2
P3
P4
V
DD
DGND
P5
P6
24 R
SET
23 COMP
22 DAC 1
21 DAC 2
20 DAC 3
19 V
18 AGND
17 PV
DD
9
P
1
A
1
S
1
S
1
C
1
R
1
P
1
E
3
3
3
2
2
D
2
2
TOP VIEW
(Not to Scale)
ADV7390/
ADV7391
0
Figure 17. ADV7390/ADV7391 Pin Configuration
TOP VIEW
(Not to Scale)
ADV7392/
ADV7393
PIN 1
1
2
3
4
5
6
7
8
9
V
DD_IO
P5
P6
V
DGP8
P910
22EXT_LF
23 PV
AA
25 V
27 DAC 2
29 COMP
SET
1
P
1
A
1
S
1
P
1
P
1
P
1
P
1
C
2
R
1
S
3
3
3
D
3
3
3
3
4
3
3S
H
V
0
Figure 18. ADV7392/ADV7393 Pin Configuration
Table 12. Pin Function Descriptions
Pin Number
ADV7390/91
ADV7392/93
9 to 7, 4 to 2,
31, 30
18 to 15, 11 to 8, 5
to 2, 39 to 37, 34
13
19
Mnemonic
P7 to P0
Input/
Output
I
Description
8-Bit Pixel Port (P7 to P0). P0 is the LSB. Refer to Table 30 for input
modes (ADV7390/ADV7391).
16-Bit Pixel Port (P15 to P0). P0 is the LSB. Refer to Table 31 for input
modes (ADV7392/ADV7393).
Pixel Clock Input for HD (74.25 MHz), ED
1
(27 MHz or 54 MHz), or
SD (27 MHz).
Horizontal Synchronization Signal. This pin can also be configured to
output an SD, ED, or HD horizontal synchronization signal. See the
External Horizontal and Vertical Synchronization Control section.
Vertical Synchronization Signal. This pin can also be configured to
output an SD, ED, or HD vertical synchronization signal. See the
External Horizontal and Vertical Synchronization Control section.
Multifunctional Pin: Subcarrier Frequency Lock (SFL) Input/SPI Data
Output (MISO). The SFL input is used to drive the color subcarrier
DDS system, timing reset, or subcarrier reset.
Controls the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For
full-drive operation (for example, into a 37.5 Ω load), a 510 Ω resistor
must be connected from R
SET
to AGND. For low drive operation (for
example, into a 300 Ω load), a 4.12 kΩ resistor must be connected
from R
SET
to AGND.
Compensation Pin. Connect a 2.2 nF capacitor from COMP to V
AA
.
DAC Outputs. Full-drive and low-drive capable DACs.
Multifunctional Pin: I
2
C Clock Input/SPI Data Input.
Multifunctional Pin: I
2
C Data Input/Output. Also, SPI clock input.
Multifunctional Pin: ALSB sets up the LSB
2
of the MPU I
2
C
address/SPI slave select (SPI_SS).
Resets the on-chip timing generator and sets the ADV739x into its
default mode.
Analog Power Supply (3.3 V).
Digital Power Supply (1.8 V). For dual-supply configurations, V
DD
can
be connected to other 1.8 V supplies through a ferrite bead or
suitable filtering.
Input/Output Digital Power Supply (3.3 V).
PLL Power Supply (1.8 V). For dual-supply configurations, PV
DD
can
be connected to other 1.8 V supplies through a ferrite bead or
suitable filtering.
P15 to P0
I
CLKIN
I
27
33
HSYNC
I/O
26
32
VSYNC
I/O
25
31
SFL/MISO
I/O
24
30
R
SET
I
23
22, 21, 20
12
11
10
29
28, 27, 26
14
13
12
COMP
DAC 1, DAC 2, DAC 3
SCL/MOSI
SDA/SCLK
ALSB/SPI_SS
O
O
I
I/O
I
14
20
RESET
I
19
5, 28
25
6, 35
V
AA
V
DD
P
P
1
17
1
23
V
DD_IO
PV
DD
P
P
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7393-DBRDZ 功能描述:BOARD EVAL FOR ADV7393 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:Advantiv® 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電信，線路接口單元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要屬性:T1/J1/E1 LIU 次要屬性:- 已供物品:板，電源，線纜，CD 其它名稱:82EBV2081
ADV7393EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
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ADV7393WBCPZ-REEL 制造商:Analog Devices 功能描述:LOW POWER, CHIP SCALE 10-BIT SD/HD VIDEO ENCODER - Tape and Reel
ADV73946603 制造商:LG Corporation 功能描述:Frame Assembly
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