參數(shù)資料
型號(hào)： ADV7392BCPZ
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述： COLOR SIGNAL ENCODER, QCC40
封裝： 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFSCP-40
文件頁(yè)數(shù)： 57/96頁(yè)
文件大?。?/td> 1209K
代理商： ADV7392BCPZ
ADV7390/ADV7391/ADV7392/ADV7393
Rev. 0 | Page 57 of 96
0
Figure 76. Input Signal to ED/HD Adaptive Filter
0
Figure 77. Output Signal from ED/HD Adaptive Filter (Mode A)
When changing the adaptive filter mode to Mode B
(Subaddress 0x35, Bit 6), the output shown in Figure 78
can be obtained.
0
Figure 78. Output Signal from ED/HD Adaptive Filter (Mode B)
SD DIGITAL NOISE REDUCTION
Subaddress 0xA3 to Subaddress 0xA5
Digital noise reduction (DNR) is applied to the Y data only.
A filter block selects the high frequency, low amplitude compo-
nents of the incoming signal (DNR input select). The absolute
value of the filter output is compared to a programmable
threshold value (DNR threshold control). There are two DNR
modes available: DNR mode and DNR sharpness mode.
In DNR mode, if the absolute value of the filter output is
smaller than the threshold, it is assumed to be noise. A
programmable amount (coring gain border, coring gain data) of
this noise signal is subtracted from the original signal. In DNR
sharpness mode, if the absolute value of the filter output is less
than the programmed threshold, it is assumed to be noise as
before. However, if the level exceeds the threshold, now being
identified as a valid signal, a fraction of the signal (coring gain
border, coring gain data) is added to the original signal to boost
high frequency components and sharpen the video image.
In MPEG systems, it is common to process the video information
in blocks of 8 pixels × 8 pixels for MPEG2 systems, or 16 pixels
× 16 pixels for MPEG1 systems (block size control). DNR can
be applied to the resulting block transition areas known to
contain noise. Generally, the block transition area contains two
pixels. It is possible to define this area to contain four pixels
(border area).
It is also possible to compensate for variable block positioning
or differences in YCrCb pixel timing with the use of the DNR
block offset.
The digital noise reduction registers are three 8-bit registers.
They are used to control the DNR processing.
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
CORING GAIN DATA
CORING GAIN BORDER
GAIN
DNR CONTROL
FILTER
OUTPUT
> THRESHOLD
INPUT FILTER
BLOCK
FILTER OUTPUT
< THRESHOLD
DNR OUT
+
+
MAIN SIGNAL PATH
ADD SIGNAL
ABOVE
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR
SHARPNESS
MODE
NOISE
SIGNAL PATH
Y DATA
INPUT
BLOCK SIZE CONTROL
BORDER AREA
BLOCK OFFSET
CORING GAIN DATA
CORING GAIN BORDER
GAIN
DNR CONTROL
FILTER
OUTPUT
< THRESHOLD
INPUT FILTER
BLOCK
FILTER OUTPUT
> THRESHOLD
DNR OUT
MAIN SIGNAL PATH
SUBTRACT
SIGNAL IN
THRESHOLD
RANGE FROM
ORIGINAL SIGNAL
DNR MODE
NOISE
SIGNAL PATH
Y DATA
INPUT
–
+
0
Figure 79. SD DNR Block Diagram
相關(guān)PDF資料
PDF描述
ADV7392BCPZ-REEL Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392EBZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393 Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393BCPZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393BCPZ-REEL Low Power, Chip Scale 10-Bit SD/HD Video Encoder
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7392BCPZ-3REEL 功能描述:Video Encoder IC DVD, Game Consoles, Media Players 40-LFCSP-WQ (6x6) 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態(tài):有效 類型:視頻編碼器 應(yīng)用:DVD，游戲控制臺(tái)，媒體播放器 電壓 - 電源，模擬:2.6 V ~ 3.46 V 電壓 - 電源，數(shù)字:1.71 V ~ 1.89 V 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:40-LFCSP-WQ（6x6） 標(biāo)準(zhǔn)包裝:2,500
ADV7392BCPZ-REEL 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392EBZ 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7392WBCPZ 制造商:Analog Devices 功能描述:
ADV7392WBCPZ-REEL 制造商:Analog Devices 功能描述:
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