參數資料
型號: ADV7391EBZ
廠商: Analog Devices, Inc.
英文描述: Low Power, Chip Scale 10-Bit SD/HD Video Encoder
中文描述: 低功耗,芯片尺寸10位標清/高清視頻編碼器
文件頁數: 29/96頁
文件大小: 1209K
代理商: ADV7391EBZ
ADV7390/ADV7391/ADV7392/ADV7393
Table 17. Register 0x31 to Register 0x33
SR7 to
SR0
Register
0x31
ED/HD Mode
Register 2
Rev. 0 | Page 29 of 96
Bit Description
ED/HD Pixel Data Valid.
Bit Number
5
4
0
1
0
1
0
1
0
0
0
0
0
1
0
1
1
0
0
0
1
Reset
Value
0x00
7
0
1
0
1
0
1
6
0
0
1
1
0
1
1
3
0
1
0
1
0
1
0
0
1
2
0
1
0
0
0
0
1
0
1
1
0
1
0
0
1
1
0
0
0 Register Setting
0
Pixel data valid off
1
Pixel data valid on
HD test pattern off
HD test pattern on
Hatch
Field/frame
Disabled
Enabled
Disabled
11 IRE
6 IRE
1.5 IRE
Disabled
Enabled
0
0 clock cycles
1
1 clock cycle
0
2 clock cycles
1
3 clock cycles
0
4 clock cycles
0 clock cycles
1 clock cycle
2 clock cycles
3 clock cycles
4 clock cycles
Disabled
Enabled
Disabled
Enabled
0
Cb after falling edge of HSYNC
1
Cr after falling edge of HSYNC
0 must be written to this bit
8-bit input
10-bit input
1
Disabled
Enabled
0 must be written to this bit
Disabled
Enabled
1 must be written to this bit
Disable
Enabled
HD Oversample Rate Select.
ED/HD Test Pattern Enable.
ED/HD Test Pattern Hatch/Field.
ED/HD Vertical Blanking Interval (VBI)
Open.
ED/HD Undershoot Limiter.
ED/HD Sharpness Filter.
0x00
ED/HD Y Delay with Respect to Falling
Edge of HSYNC.
ED/HD Color Delay with Respect to
Falling Edge of HSYNC.
ED/HD CGMS Enable.
0x32
ED/HD Mode
Register 3
ED/HD CGMS CRC Enable.
0x68
ED/HD Cr/Cb Sequence.
Reserved.
ED/HD Input Form
at.
Sinc Compensation Filter on DAC 1,
DAC 2, DAC 3.
Reserved.
ED/HD Chroma SSAF Filter.
Reserved.
ED/HD Double Buffering.
0x33
ED/HD Mode
Register 4
1
Available on the ADV7392/ADV7393 (40-pin devices) only.
相關PDF資料
PDF描述
ADV7392 Low Power, Chip Scale 10-Bit SD/HD Video Encoder
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ADV7392EBZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder
ADV7393 Low Power, Chip Scale 10-Bit SD/HD Video Encoder
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ADV7391WBCPZ 制造商:Analog Devices 功能描述:
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