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參數(shù)資料
| 型號(hào)： | ADV7391BCPZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| 中文描述： | COLOR SIGNAL ENCODER, QCC32 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFSCP-32 |
| 文件頁(yè)數(shù)： | 91/96頁(yè) |
| 文件大小： | 1209K |
| 代理商： | ADV7391BCPZ-REEL |
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ADV7390/ADV7391/ADV7392/ADV7393
Table 96. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x10
ED-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Rev. 0 | Page 91 of 96
Table 97. 16-Bit 625p YCrCb In, RGB Out
Subaddress
Setting Description
0x17
0x02
0x00
0x1C
0x01
0x10
0x02
0x10
Software reset.
All DACs enabled. PLL enabled (8×).
ED-SDR input mode.
RGB output enabled. RGB output sync
enabled.
625p @ 50 Hz. HSYNC/VSYNC synch-
ronization. EIA-770.2 output levels.
Pixel data valid.
0x30
0x18
0x31
0x01
Table 98. 8-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 99. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 100. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 101. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x04
525p @ 59.94 Hz. EAV/SAV synchro-
nization. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
Table 102. 8-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
Table 103. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (8×).
0x01
0x20
ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x30
0x1C
625p @ 50 Hz. EAV/SAV synchroniza-
tion. EIA-770.2 output levels.
0x31
0x01
Pixel data valid.
0x33
0x6C
10-bit input enabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADV7391EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392 | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392BCPZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392BCPZ-REEL | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392EBZ | Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADV7391EBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7391WBCPZ | 制造商:Analog Devices 功能描述: |
| ADV7391WBCPZ-RL | 制造商:Analog Devices 功能描述: |
| ADV7392 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Power, Chip Scale 10-Bit SD/HD Video Encoder |
| ADV7392BCPZ | 制造商:Analog Devices 功能描述: |
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