參數(shù)資料
型號(hào)： ADV7320KSTZ
廠商： ANALOG DEVICES INC
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
中文描述： COLOR SIGNAL ENCODER, PQFP64
封裝： LEAD FREE, PLASTIC, MS-026BCD, LQFP-64
文件頁(yè)數(shù)： 39/88頁(yè)
文件大?。?/td> 1002K
代理商： ADV7320KSTZ
ADV7320/ADV7321
optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and
S_BLANK. HD syncs are input on Pins P_VSYNC, P_HSYNC,
and P_BLANK.
Rev. 0 | Page 39 of 88
CLKIN_A
CLKIN_B
MPEG2
DECODER
3
27MHz
10
YCrCb
INTERLACED TO
PROGRESSIVE
10
CrCb
10
Y
3
27MHz
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7320/
ADV7321
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 51. Simultaneous PS and SD Input
CLKIN_A
CLKIN_B
SDTV
DECODER
3
27MHz
10
YCrCb
10
CrCb
10
Y
3
74.25MHz
1080i
OR
720p
OR
1035i
S[9:0]
C[9:0]
Y[9:0]
P_VSYNC,
P_HSYNC,
P_BLANK
ADV7320/
ADV7321
HDTV
DECODER
0
S_VSYNC,
S_HSYNC,
S_BLANK
Figure 52. Simultaneous HD and SD Input
In simultaneous SD/HD input mode, if the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the clock align
bit [Address 0x01, Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
clock align bit must be set because the phase difference between
both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
0
t
DELAY
<
9.25ns OR
t
DELAY
>
27.75ns
Figure 53. Clock Phase with Two Input Clocks
PROGRESSIVE SCAN AT 27 MHZ (DUAL EDGE)
OR 54 MHZ
Address[0x01]: Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or
54 MHz. The input data is interleaved onto a single 8-/10-bit
bus and is input on Pins Y9 to Y0. When a 27 MHz clock is
supplied, the data is clocked in upon the rising and falling edges
of the input clock, and the clock edge bit [Address 0x01, Bit 1]
must be set accordingly.
Table 22 provides an overview of all possible input configurations.
Figure 54, Figure 55, and Figure 56 show the possible conditions:
Cb data on the rising edge, and Y data on the rising edge.
3FF
00
00
XY
Y0
Y1
Cr0
CLKIN_B
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Y9–Y0
Cb0
0
Figure 54. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
3FF
00
00
XY
Cb0
Cr0
Y1
CLKIN_B
Y9–Y0
Y0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
0
Figure 55. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
PIXEL INPUT
DATA
3FF
00
00
XY
Cb0
Y0
Y1
Cr0
CLKIN_B
WITH A 54MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
0
Figure 56. Input Sequence in PS Bit Interleaved Mode (EAV/SAV)
MPEG2
DECODER
CLKIN_A
Y[9:0]
INTERLACED
TO
PROGRESSIVE
YCrCb
10
3
27MHz OR 54MHz
YCrCb
ADV7320/
ADV7321
P_VSYNC,
P_HSYNC,
P_BLANK
0
Figure 57. 10-Bit PS at 27 MHz or 54 MHz
相關(guān)PDF資料
PDF描述
ADV7320 Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7321 Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7321KSTZ Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7324 Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
ADV7324KSTZ Multiformat 216 MHz Video Encoder with Six NSV 14-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADV7321 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 216 MHz Video Encoder with Six NSV 12-Bit DACs
ADV7321KST 制造商:Analog Devices 功能描述:VID ENCODER 6DAC 12-BIT 64LQFP - Bulk
ADV7321KSTZ 功能描述:IC VID ENC 6-12BIT DAC'S 64LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編碼器，解碼器，轉(zhuǎn)換器 系列:- 產(chǎn)品變化通告:Development Systems Discontinuation 26/Apr/2011 標(biāo)準(zhǔn)包裝:1 系列:- 類型:編碼器 應(yīng)用:DVB-S.2 系統(tǒng) 電壓 - 電源，模擬:- 電壓 - 電源，數(shù)字:- 安裝類型:- 封裝/外殼:模塊 供應(yīng)商設(shè)備封裝:模塊 包裝:散裝 其它名稱:Q4645799
ADV7322 制造商:AD 制造商全稱:Analog Devices 功能描述:Multiformat 11-Bit HDTV Video Encoder
ADV73225709 制造商:LG Corporation 功能描述:Frame Assembly
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